Memory Devices and Method of Fabricating Same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
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Abstract
A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.
Claims20
An apparatus comprising:
- a control gate structure and a memory gate structure over a substrate;
- a charge storage layer formed between the control gate structure and the memory gate structure, the charge storage layer extending between the memory gate structure and the substrate;
- a first spacer along a sidewall of the memory gate structure, an upper surface of the memory gate structure being recessed lower than an upper surface of the first spacer;
- one or more second spacers along a sidewall of the first spacer, at least one of the one or more second spacers covering the upper surface of the memory gate structure;
- a first drain/source region formed in the substrate and adjacent to the memory gate structure;
- and
- a second drain/source region formed in the substrate and adjacent to the control gate structure.
A device comprising:
- a control gate structure over a substrate;
- an L-shaped charge storage structure adjacent the control gate structure;
- a memory gate structure on the L-shaped charge storage structure, the L-shaped charge storage structure being interposed between the control gate structure and the memory gate structure;
- a first spacer along a sidewall of the memory gate structure, the first spacer completely covering a sidewall of the memory gate structure;
- and
- one or more dielectric spacers adjacent to the first spacer, the first spacer being interposed between the one or more dielectric spacers and the memory gate structure, at least a portion of the one or more dielectric spacers directly contacting an upper surface of the memory gate structure.
A device comprising:
- a control gate structure over a substrate;
- a memory gate structure over the substrate;
- an L-shaped silicon nitride layer interposed between the control gate structure and the memory gate structure;
- a first spacer along a sidewall of the memory gate structure, wherein a lowest point of an upper surface of the memory gate structure extends lower than an upper surface of the first spacer;
- a second spacer along a sidewall of the first spacer and an upper surface of the memory gate structure, wherein the second spacer directly contacts the upper surface of the memory gate structure;
- a first drain/source region formed in the substrate and adjacent to the memory gate structure;
- and
- a second drain/source region formed in the substrate and adjacent to the control gate structure.
Dependencies are inferred from the claim text.