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US 2020/0266202 A1Published application
3-D NAND Control Gate Enhancement
AssigneeApplied Materials, Inc.
InventorsThomas Kwon, Xinhai Han
Life of this patent
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Abstract
Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.
Claims20
A NAND memory structure comprising:
- a control gate material and a floating gate material disposed between a first insulating layer and a second insulating layer, the floating gate material having a first side, a second side, a third side, and a fourth side, the second side facing the control gate material and the fourth side facing a memory hole channel;
- a conformal blocking oxide liner along the first side, the second side, and the third side of the floating gate material and along a face of the first and second insulating layers facing the memory hole channel, such that the conformal blocking oxide liner electrically isolates the control gate material from the floating gate material;
- a gate oxide material contacting the fourth side of the floating gate material and the conformal blocking oxide liner adjacent the face of the first and second insulating layers;
- and
- a silicon material on the gate oxide material, a surface of the silicon material facing the memory hole channel.
2 more elements
A method of forming a NAND memory structure, the method comprising:
- depositing a plurality of alternating layers of a nitride material and an oxide material separated by a silicon layer;
- etching a memory hole through the plurality of alternating layers to form an exposed surface of the plurality of alternating layers;
- selectively etching a portion of the nitride material through the memory hole;
- depositing a blocking oxide layer in the memory hole to form a conformal oxide liner on the exposed surface of the plurality of alternating layers;
- depositing a floating gate metal into the memory hole to form a floating gate adjacent the conformal oxide liner;
- depositing a gate oxide material into the memory hole to form a layer of gate oxide material adjacent the floating gate;
- depositing a silicon material in the memory hole to form a silicon channel adjacent the layer of gate oxide material;
- removing the nitride material to expose the silicon layers and the conformal oxide liner to form a gap on an opposite side of the conformal oxide liner from the floating gate;
- removing the silicon layers to expose layers of oxide material;
- and
- depositing a metal gate material to fill the gap between layers of the oxide material.
8 more elements
A processing tool comprising:
- a central transfer station comprising a robot configured to move a wafer;
- plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations, the plurality of process stations comprising a blocking oxide material deposition chamber;
- and
- a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the wafer between process stations, and to control a process occurring in each of the process stations.
1 more element
Dependencies are inferred from the claim text.