# US 2020/0266201 A1 · Semiconductor structure, static random access memory and fabrication method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2020/0266201 A1
- Document ID: US20200266201A1
- Status: Published application
- Kind: A1
- Application number: 16/870,044
- Filed: 2020-05-08
- Published: 2020-08-20
- Earliest claimed: 2016-11-28
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Yong LI
- Web page: https://patentgrep.com/patent/US20200266201A1

## CPC

- H10B 10/12: {comprising a MOSFET load element}
- G11C 11/4023: {using field effect transistors}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/83125: {the IGFETs characterised by having shared source or drain regions}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a static random access memory are provided. The semiconductor structure includes a base substrate. The base substrate includes a substrate and a plurality of discrete fins on the substrate. The substrate includes a pass gate transistor region. The semiconductor structure further includes a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin, and pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region. At least one of the pass gate doped regions on one side of the gate structure is a non-epitaxial layer doped region in the fin.

## Claims

### Claim 1

A semiconductor structure, comprising:
a base substrate, including a substrate and a plurality of discrete fins on the substrate, wherein the substrate includes a pass gate transistor region;
a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin; and
pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region, wherein at least one of the pass gate doped regions on one side of the gate structure is a non-epitaxial layer doped region in the fin.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the pass gate transistor region includes an NMOS region; and
the pass gate doped regions include N-type ions.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein:
doped ions in the pass gate doped regions include P ions and As ions;
a doping concentration of the P ions is in a range of approximately 1×1015 atoms/cm3-2×1015 atoms/cm3; and
a doping concentration of the As ions is in a range of approximately 1×1015 atoms/cm3-4×1015 atoms/cm3.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the pass gate doped region in the fin on one side of the gate structure in the pass gate transistor region is the non-epitaxial layer doped region; and
the pass gate doped region in the fin on the other side of the gate structure in the pass gate transistor region is an epitaxial layer doped region.

### Claim 5 (depends on 4)

The semiconductor structure according to claim 4, wherein:
the epitaxial layer doped region is made of SiP; and
a concentration of the P ions in the pass gate doped region is in a range of approximately 1×1020 atoms/cm3-2×1021 atoms/cm3.

### Claim 6 (depends on 1)

The semiconductor structure according to claim 1, wherein:
the pass gate transistor region includes a first pass gate transistor region and a second pass gate transistor region, adjacent to each other along a direction perpendicular to a length direction of the fin;
the gate structure in the first pass gate transistor region is across the fin in the first pass gate transistor region, and the gate structure in the second pass gate transistor region is across the fin in the second pass gate transistor region;
the pass gate doped region in the fin on one side of the gate structure in the first pass gate transistor region is the non-epitaxial layer doped region; and
the pass gate doped regions in the fin on the other side of the gate structure in the first pass gate transistor region and in the fin on both sides of the gate structure in the second pass gate transistor region are the epitaxial layer doped regions.

### Claim 7 (depends on 1)

The semiconductor structure according to claim 1, wherein:
at least one of the pass gate doped regions has an ion-doped non-epitaxial layer on one side of the gate structure on at least one fin, a no ion-doped epitaxial layer at least on the one side of the gate structure on the at least one fin, and remaining pass gate doped regions have ion-doped epitaxial layers on each fin.

### Claim 8

A static random access memory (SRAM), comprising:
a semiconductor structure, including:
a base substrate, including a substrate and a plurality of discrete fins on the substrate, wherein the substrate includes a pass gate transistor region;
a gate structure, across a length portion of each fin, covering top and sidewall surfaces of each fin, and on each fin; and
pass gate doped regions in the fin on both sides of the gate structure in the pass gate transistor region, wherein at least one of the pass gate doped regions on one side of the gate structure is a non-epitaxial layer doped region in the fin.

### Claim 9 (depends on 8)

The static random access memory (SRAM) according to claim 8, wherein:
the pass gate doped region in the fin on one side of the gate structure in the pass gate transistor region is the non-epitaxial layer doped region; and
the pass gate doped region in the fin on the other side of the gate structure in the pass gate transistor region is an epitaxial layer doped region.

### Claim 10 (depends on 9)

The static random access memory (SRAM) according to claim 9, wherein:
the epitaxial layer doped region is made of SiP; and
a concentration of the P ions in the pass gate doped region is in a range of approximately 1×1020 atoms/cm3-2×1021 atoms/cm3.

### Claim 11 (depends on 8)

The static random access memory (SRAM) according to claim 8, wherein:
the pass gate transistor region includes a first pass gate transistor region and a second pass gate transistor region, adjacent to each other along a direction perpendicular to a length direction of the fin;
the gate structure in the first pass gate transistor region is across the fin in the first pass gate transistor region, and the gate structure in the second pass gate transistor region is across the fin in the second pass gate transistor region;
the pass gate doped region in the fin on one side of the gate structure in the first pass gate transistor region is the non-epitaxial layer doped region; and
the pass gate doped regions in the fin on the other side of the gate structure in the first pass gate transistor region and in the fin on both sides of the gate structure in the second pass gate transistor region are the epitaxial layer doped regions.

### Claim 12 (depends on 8)

The static random access memory (SRAM) according to claim 8, wherein:
the pass gate transistor region includes an NMOS region; and
the pass gate doped regions include N-type ions.

### Claim 13 (depends on 8)

The static random access memory (SRAM) according to claim 8, wherein:
doped ions in the pass gate doped regions include P ions and As ions;
a doping concentration of the P ions is in a range of approximately 1×1015 atoms/cm3-2×1015 atoms/cm3; and
a doping concentration of the As ions is in a range of approximately 1×1015 atoms/cm3-4×1015 atoms/cm3.

### Claim 14 (depends on 8)

The static random access memory (SRAM) according to claim 8, wherein:
at least one of the pass gate doped regions has an ion-doped non-epitaxial layer on one side of the gate structure on at least one fin, a no ion-doped epitaxial layer at least on the one side of the gate structure on the at least one fin, and remaining pass gate doped regions have ion-doped epitaxial layers on each fin.