Semiconductor device and a method of manufacturing the same

A semiconductor device comprising:

• a first voltage device region over a substrate;
• a second voltage device region over the substrate;
• and
• a first deep well common to the first and second voltage device regions, wherein:
• an operation voltage of electronic devices in the second voltage device region is higher than the operation voltage of electronic devices in the first voltage device region,
• the first deep well has a first conductivity type,
• the first voltage device region includes a first well having a second conductivity type and a second well having the first conductivity type,
• the second voltage region includes a third well having the second conductivity type and a fourth well having the first conductivity type,
• a second deep well having the second conductivity type is formed below the second well, a third deep well having the second conductivity type and disposed below the fourth well,
• each of the first, second, third and fourth wells comprises at least one transistor,
• the first and third wells are in contact with the first deep well, and
• a bottom and sides of the second deep well are directly connected to the first deep well and a bottom and sides of the third deep well are directly connected to the first deep well.

A semiconductor device comprising:

• a first deep well having a first conductivity type,
• a first well having the second conductivity type and directly connected to the first deep well;
• a second well having the first conductivity type and directly connected to the first deep well;
• a third well having the second conductivity type and directly connected to the first deep well;
• a fourth well having the first conductivity type;
• a second deep well having the second conductivity type and disposed below the fourth well;
• and
• a third deep well having the second conductivity type and disposed below the fourth well, wherein:
• the second well is separated by the second deep well from the first deep well,
• the fourth well is separated by the third deep well from the first deep well,
• each of the first, second, third and fourth wells comprises at least one transistor, and
• a bottom and sides of the second deep well are directly connected to the first deep well, and a bottom and sides of the third deep well are directly connected to the first deep well.