Semiconductor Arrangement and Method for Producing a Semiconductor Arrangement
AssigneeInfineon Technologies AG
InventorMichael Stadler
Life of this patent
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Abstract
A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.
Claims19
A semiconductor arrangement, comprising:
- a lower semiconductor chip;
- an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip;
- a metallization layer arranged on the upper main side of the lower semiconductor chip;
- and
- a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip,
- wherein the metallization layer comprises a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.
A semiconductor arrangement, comprising:
- a lower semiconductor chip;
- an upper semiconductor chip over an upper main side of the lower semiconductor chip;
- a metallization layer arranged on the upper main side of the lower semiconductor chip;
- and
- a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip,
- wherein the metallization layer comprises surface structuring having a plurality of depressions,
- wherein the surface structuring is arranged along a contour of the upper semiconductor chip.
A method for producing a semiconductor arrangement, the method comprising:
- applying a metallization layer on an upper main side of a lower semiconductor chip,
- structuring the metallization layer;
- and
- fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material,
- wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer,
- wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.
Dependencies are inferred from the claim text.