Semiconductor device
AssigneeToshiba Memory Corporation
InventorsYasuhiro HIRASHIMA, Masaru KOYANAGI, Mikihiko ITO, Kei SHIRAISHI, Fumiya WATANABE
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Abstract
A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.
Claims12
A semiconductor memory device comprising:
- a memory cell array including a plurality of memory cells each configured to store data;
- an input circuit that includes:
- a first comparator configured to output a first output signal based on a comparison result of a first input signal and a first reference signal,
- a second comparator configured to output a second output signal based on a comparison result between a second input signal and a second reference signal,
- a third comparator configured to output a third output signal based on a comparison result between a third input signal and a third reference signal,
- an inverter connected between an output node of the second comparator and an output node of the third comparator, and
- a data latch circuit configured to latch the first output signal using the second output signal or the third output signal;
- and
- a control circuit configured to switch the inverter on and off,
- wherein a duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal respectively.
The semiconductor memory device, wherein the first comparator includes:
- an amplification circuit that includes a first transistor having a gate to which the first input signal is supplied, a second transistor having a gate to which the first reference signal is supplied, and a first current source having an output terminal commonly connected to a first terminal of each of the first transistor and the second transistor via a first node,
- a first current mirror circuit that includes a first terminal connected to a second terminal of the first transistor,
- a second current mirror circuit that includes a first terminal connected to a second terminal of the second transistor, and
- a third current mirror circuit that includes a first terminal connected to a second terminal of the first current mirror circuit and a second terminal connected a second terminal of the second current mirror circuit.
Dependencies are inferred from the claim text.