Semiconductor system capable of scrambling addresses
AssigneeSK hynix Inc.
InventorJi Hyae BAE
Life of this patent
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Abstract
A semiconductor system in accordance with an embodiment includes a module controller and a plurality of semiconductor chips configured to receive logical addresses from the module controller. The semiconductor system also includes a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips. Each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.
Claims17
A semiconductor system comprising:
- a module controller;
- a plurality of semiconductor chips configured to receive logical addresses from the module controller;
- and
- a plurality of scramble circuits, with a scramble circuit provided for each of the plurality of semiconductor chips, configured to receive the logical addresses and to output corresponding physical addresses for the plurality of semiconductor chips, wherein each scramble circuit of the plurality of scramble circuits is configured to receive the same logical address and to output a corresponding physical address different from the physical addresses output by the other scramble circuits of the plurality of scramble circuits.
A semiconductor system comprising:
- a module substrate;
- a plurality of semiconductor chips mounted on the module substrate;
- a module controller configured to provide each of the semiconductor chips with logical addresses and address bit test commands;
- and
- scramble circuits, with a scramble circuit provided for each of the semiconductor chips, the scramble circuits configured to convert the logical addresses into physical addresses based on the address bit test commands,
- wherein the scramble circuits are configured to generate a different physical addresses for each semiconductor chip given the same logical address.
Dependencies are inferred from the claim text.