Memory device and system

A memory device comprising:

• a first nonvolatile memory and a second nonvolatile memory;
• a processor which receives an identifier, first data associated with the identifier, and a write request for the first data, and generates a first logical address, using the identifier;
• and
• an address generator which generates a first physical address corresponding to the first logical address, and a second physical address corresponding to the first logical address and different from the first physical address, wherein:
• in response to a write request for the first data:
• the processor stores the first data at the first physical address of the first nonvolatile memory, and
• the processor stores the first data at the second physical address of the second nonvolatile memory.

A memory device comprising:

• a first nonvolatile memory which stores first data at a first physical address corresponding to a first identifier;
• a second nonvolatile memory in which second data different from the first data is stored at a second physical address corresponding to the first identifier and different from the first physical address;
• an attack detecting circuit which detects whether the first nonvolatile memory and the second nonvolatile memory are attacked;
• and
• a processor which receives a read request of data corresponding to the first identifier, wherein in response to the read request:
• the processor accesses the first physical address of the first nonvolatile memory to read third data associated with the first data,
• the processor accesses the second physical address of the second nonvolatile memory to read fourth data associated with the second data, and
• the attack detecting circuit receives the third and fourth data, and determines whether the first nonvolatile memory and the second nonvolatile memory are attacked based on the third and fourth data.