Directed interrupt for multilevel virtualization with interrupt table

A computer system for providing an interrupt signal to a first guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the first guest operating system, the computer system comprising:

• a memory;
• and
• a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
• receiving, by a bus attachment device from one bus connected module of a plurality of bus connected modules operationally coupled to the plurality of processors via the bus attachment device, an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by the first guest operating system as a target processor to handle the interrupt signal, the first guest operating system implemented using a second guest operating system as a host hosting the first guest operating system;
• retrieving, by the bus attachment device, a copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table stored in a first memory section of a memory operationally connected with the bus attachment device, the first memory section being assigned to the second guest operating system, and the copy of the interrupt table entry comprising a mapping of the interrupt target ID to a logical processor ID;
• translating, by the bus attachment device, the interrupt target ID to the logical processor ID using the copy of the interrupt table entry;
• and
• forwarding, by the bus attachment device, the interrupt signal to the target processor to handle, the forwarding using the logical processor ID resulting from the translating to address the target processor directly.

A computer-implemented method of providing an interrupt signal to a first guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the first guest operating system, the computer-implemented method comprising:

• receiving, by a bus attachment device from one bus connected module of a plurality of bus connected modules operationally coupled to the plurality of processors via the bus attachment device, an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by the first guest operating system as a target processor to handle the interrupt signal, the first guest operating system implemented using a second guest operating system as a host hosting the first guest operating system;
• retrieving, by the bus attachment device, a copy of an interrupt table entry assigned to the interrupt target ID from an interrupt table stored in a first memory section of a memory operationally connected with the bus attachment device, the first memory section being assigned to the second guest operating system, and the copy of the interrupt table entry comprising a mapping of the interrupt target ID to a logical processor ID;
• translating, by the bus attachment device, the interrupt target ID to the logical processor ID using the copy of the interrupt table entry;
• and
• forwarding, by the bus attachment device, the interrupt signal to the target processor to handle, the forwarding using the logical processor ID resulting from the translating to address the target processor directly.