Directed interrupt virtualization

A computer system for providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer system comprising:

• a memory;
• and
• a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising:
• receiving, by a bus attachment device of the computer system from a bus connected module of a plurality of bus connected modules operationally coupled to the plurality of processors via the bus attachment device, an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by the guest operating system as a target processor for handling the interrupt signal;
• translating, by the bus attachment device, the interrupt target ID to a logical processor ID of the target processor using a mapping table of the bus attachment device, the mapping table mapping interrupt target IDs of the processors assigned for usage by the guest operating system to logical processor IDs of the plurality of processors;
• and
• forwarding, by the bus attachment device, the interrupt signal to the target processor to handle, the forwarding using the logical processor ID of the target processor to address the target processor directly.

A computer-implemented method of providing an interrupt signal to a guest operating system executed using one or more processors of a plurality of processors of a computer system assigned for usage by the guest operating system, the computer-implemented method comprising:

• receiving, by a bus attachment device of the computer system from a bus connected module of a plurality of bus connected modules operationally coupled to the plurality of processors via the bus attachment device, an interrupt signal with an interrupt target ID, the interrupt target ID identifying one processor of the plurality of processors assigned for usage by the guest operating system as a target processor for handling the interrupt signal;
• translating, by the bus attachment device, the interrupt target ID to a logical processor ID of the target processor using a mapping table of the bus attachment device, the mapping table mapping interrupt target IDs of the processors assigned for usage by the guest operating system to logical processor IDs of the plurality of processors;
• and
• forwarding, by the bus attachment device, the interrupt signal to the target processor to handle, the forwarding using the logical processor ID of the target processor to address the target processor directly.