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US 2020/0264884 A1Published application
Memory apparatus and data processing system including the same
AssigneeSK hynix Inc.
InventorJong Ho JUNG
Life of this patent
Estimating the term…
Abstract
A memory apparatus may include at least one memory, and a memory controller configured to receive an address signal and a command through shared pins and store data, provided from an external source, within the memory controller when a write command is inputted without the address signal.
Claims16
A memory apparatus comprising:
- at least one memory;
- and
- a memory controller configured to receive an address signal and a command through shared pins and store data, provided from an external source, within the memory controller when a write command is inputted without the address signal.
A memory apparatus comprising:
- at least one memory;
- and
- a memory controller configured to control the at least one memory,
- wherein the memory controller comprises:
- a command decoder configured to generate a write command, an address recognition command, or a mode register command by decoding a command/address signal provided through shared pins according to a clock signal;
- a flip-flop configured to latch the write command according to the clock signal;
- a mode register set configured to generate a training mode signal according to the mode register command;
- a first logic circuit configured to perform a logic operation on the address recognition command and the training mode signal and output an output signal;
- and
- a second logic circuit configured to generate an internal write signal according to the signal latched in the flip-flop and the output signal of the first logic circuit.
7 more elements
A data processing system comprising:
- a memory apparatus, including at least one memory and a memory controller, for controlling the at least one memory and configured to receive an address signal and a command through shared pins and configured to store data provided from a host in the at least one memory or the memory controller when a write command is received by the memory controller,
- wherein the host is configured to provide the memory apparatus with the write command, without the address signal, in a training operation of the memory apparatus.
Dependencies are inferred from the claim text.