Atomic memory operation having selectable location of performance

A processing unit for a data processing system including a memory controller coupled to a system memory, the processing unit comprising:

• a processor core;
• and
• a cache memory including an arithmetic logic unit (ALU), wherein the cache memory is configured to perform:
• receiving, from the processor core, an atomic memory operation (AMO) request specifying a target address of a data granule to be updated by an AMO and a location indication;
• based on the location indication having a first setting, performing the AMO indicated by the AMO request in the cache memory utilizing the ALU;
• and
• based on the location indication having a different second setting, the cache memory issuing to the memory controller the AMO request to cause the AMO to be performed at the memory controller.

A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• a processing unit for a data processing system including a memory controller coupled to a system memory, the processing unit including:
• a processor core;
• and
• a cache memory including an arithmetic logic unit (ALU), wherein the cache memory is configured to perform:
• receiving, from the processor core, an atomic memory operation (AMO) request specifying a target address of a data granule to be updated by an AMO and a location indication;
• based on the location indication having a first setting, performing the AMO indicated by the AMO request in the cache memory utilizing the ALU;
• and
• based on the location indication having a different second setting, the cache memory issuing to the memory controller the AMO request to cause the AMO to be performed at the memory controller.