Nonvolatile semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsKenichiro YOSHII, Shinichi KANNO
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Abstract
According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
Claims27
A nonvolatile semiconductor memory device connectable to a controller, comprising:
- a cell array including a plurality of blocks;
- and
- a control circuit configured to execute program operations for a plurality of pages included in a write destination block of the blocks in a certain program order, the write destination block being selected by the controller from the blocks, wherein
- the control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
A nonvolatile semiconductor memory device connected to a first semiconductor device, the nonvolatile semiconductor memory device comprising:
- a plurality of blocks each including a plurality of memory cells, wherein
- the nonvolatile semiconductor memory device is configured to:
- send, in response to receiving from the first semiconductor device a first address signal indicative of one block selected from the blocks, a second address signal selected on the basis of the received first address signal, to the first semiconductor device;
- and
- in response to receiving a command from the first semiconductor device, the command designating the first address signal, the second address signal and first data, program the first data to a memory cell corresponding to a first address which is determined based on the first address signal and the second address signal.
Dependencies are inferred from the claim text.