Memory array element sparing

A system comprising:

• a processor communicatively coupled to a memory, the processor configured to:
• store a row number and a column number that are associated with a defective memory array element of a plurality of memory array elements, wherein the plurality of memory array elements are logically arranged in a plurality of rows and a plurality of columns;
• receive a command to access a cache line, the cache line corresponding to a selected row of memory array elements of the plurality of memory array elements;
• and
• responsive to determining that the selected row matches the row number that is associated with the defective memory array element, activate, based on the column number that is associated with the defective memory array element, one or more column shifters to prevent access to the defective memory array element and provide access to a spare memory array element when accessing the cache line by sequentially shifting access away from the defective memory array element through one or more adjacent columns in the plurality of columns until reaching an associated column for the spare memory array element.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith the program instructions executable by a computer processor to cause the computer processor to perform a method comprising:

• storing a row number and a column number that are associated with a defective memory array element of a plurality of memory array elements, wherein the plurality of memory array elements are logically arranged in a plurality of rows and a plurality of columns;
• receiving a command to access a cache line, the cache line corresponding to a selected row of memory array elements of the plurality of memory array elements;
• and
• responsive to determining that the selected row matches the row number that is associated with the defective memory array element, activating, based on the column number that is associated with the defective memory array element, one or more column shifters to prevent access to the defective memory array element and provide access to a spare memory array element when accessing the cache line by sequentially shifting access away from the defective memory array element through one or more adjacent columns in the plurality of columns until reaching an associated column for the spare memory array element.