Method and system for clock synchronization based on time based control

A system of clock synchronization within an electronic device, the system comprising:

• a processor;
• and
• a memory operatively coupled to the processor, wherein the memory comprises processor instructions, which when executed by the processor, cause the processor to:
• compare a current value of a cumulative phase difference between a signal generated by a device clock in the electronic device and a reference signal generated by a master clock with a reset threshold;
• generate a control value, when the current value is greater than the reset threshold, wherein to generate the control value, the processor instructions are further configure to:
• compute a startup correction value based on a time lapsed after reset of the device clock;
• compute a dynamic correction value based on an accuracy factor associated with the device clock, a clock constant, and a comparison of a current phase difference between the signal and the reference signal with a high error threshold;
• and
• compute the control value based on the startup correction value, the dynamic correction value, and the current value of the cumulative phase difference;
• and
• adjust a frequency of the device clock based on the control value.

A non-transitory computer-readable storage medium having stored thereon, a set of computer-executable instructions causing an electronic device comprising one or more processors to perform steps comprising:

• comparing a current value of a cumulative phase difference between a signal generated by a device clock in the electronic device and a reference signal generated by a master clock with a reset threshold;
• generating a control value, when the current value is greater than the reset threshold, wherein generating the control value comprises:
• computing a startup correction value based on a time lapsed after reset of the device clock;
• computing a dynamic correction value based on an accuracy factor associated with the device clock, a clock constant, and a comparison of a current phase difference between the signal and the reference signal with a high error threshold;
• and
• computing the control value based on the startup correction value, the dynamic correction value, and the current value of the cumulative phase difference;
• and
• adjusting a frequency of the device clock based on the control value.