Computer Architecture Allowing Recycling of Instruction Slack Time
AssigneeWisconsin Alumni Research Foundation
InventorsGokul Subramanian Ravi, Mikko H. Lipasti
Life of this patent
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Abstract
A computer architecture suitable for out-of-order processors manages the problem of timing slack, in which an instruction completes before its clock cycle, by recycling that slack to allow the next succeeding instruction allowing that instruction to begin execution earlier. This recycling mechanism is enabled through the use of a transparent gating between execution units which allows data transfer before clock cycle boundaries and, in some cases, by aggressively issuing children instructions contemporaneously with their parent instruction after a grandparent instruction is issued.
Claims17
A computer architecture comprising:
- a clock for generating clock cycles for synchronizing operation of the computer architecture components;
- a set of execution units (EUs) operable in parallel to execute computer instructions;
- and
- transmission gates receiving the clock cycles and each positioned to receive an output of an EU for transmission to an input of another EU, each given a transmission gate operating in a first mode to allow communication between a corresponding first and second EU only at boundaries between clock cycles and in the second mode to allow communication between the first and second EU between boundaries of clock cycles and switch from the first mode to the second mode on clock cycle boundaries;
- and
- a scheduling circuit scheduling instructions for execution on EUs according to data dependencies and wherein each given transmission gate receives a mode signal switching the given transmission gate to the second state when a parent instruction is being executed on the corresponding first EU and will complete within a current clock cycle, wherein the instruction on the corresponding second EU is a child instruction dependent on the parent instruction for data.
The computer architecture of claim 4 wherein the mode signal from the scheduling circuit further switches the given transmission gate to the second state when a grandparent instruction is being executed and will complete within the current clock cycle, wherein the parent instruction is dependent on the grandparent instruction for data.
Dependencies are inferred from the claim text.