Controller area network (can) transceiver
AssigneeTexas Instruments Incorporated
InventorsDeep BANERJEE, Lokesh Kumar GUPTA, Abhijeeth AAREY PREMANATH, Richard Sterling BROUGHTON
Life of this patent
Estimating the term…
Abstract
A bus transceiver circuit including a current source device, a current mirror coupled to the current source device, and a first transistor having a first control input and first and second current terminals. The bus transceiver circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the first control input at a first node. The fourth current terminal is coupled to the current mirror. A resistor is coupled between the first current terminal and the first node.
Claims20
A bus transceiver circuit, comprising:
- a current source device;
- a current mirror coupled to the current source device;
- a first transistor having a first control input and first and second current terminals;
- a second transistor having a second control input and third and fourth current terminals, the third current terminal coupled to the first control input at a first node, and the fourth current terminal coupled to the current mirror;
- and
- a resistor coupled between the first current terminal and the first node.
A bus transceiver circuit, comprising:
- a current mirror;
- a first transistor having a first control input and first and second current terminals;
- a second transistor having a second control input and third and fourth current terminals, the third current terminal coupled to the first control input at a first node, and the fourth current terminal coupled to the current mirror;
- a resistor coupled between the first current terminal and the first node;
- and
- a Zener diode coupled between the first current terminal and the first node.
A bus transceiver circuit, comprising:
- a current source device;
- a current mirror coupled to the current source device;
- a first transistor having a first control input and first and second current terminals;
- a second transistor having a second control input and third and fourth current terminals, the third current terminal coupled to the first control input at a first node, and the fourth current terminal coupled to the current mirror;
- a resistor coupled between the first current terminal and the first node;
- a voltage clamp device coupled between the first current terminal and the first node;
- wherein the second current terminal is adapted to be coupled to a bus;
- wherein the second control input is adapted to receive a transmit signal;
- and
- wherein, while in a recessive state, the first transistor is configured to be off.
Dependencies are inferred from the claim text.