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US 2020/0264231 A1Published application
Testing of semiconductor chips with microbumps
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Wu, Hsien-Pin Hu, Shang-Yun Hou, Shin-Puu Jeng, Chen-Hua Yu, Chao-Hsiang Yang
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Abstract
A device includes a test pad on a chip. A first microbump has a first surface area that is less than a surface area of the test pad. A first conductive path couples the test pad to the first microbump. A second microbump has a second surface area that is less than the surface area of the test pad. A second conductive path couples the test pad to the second microbump.
Claims21
1-20. (canceled)
A device comprising:
- a test pad on a chip, the test pad being quadrilateral in shape;
- a first microbump pad having a first surface area that is less than a surface area of the test pad, the first microbump pad being arranged proximate to a first edge of the quadrilateral.
A device comprising:
- a test pad on a chip, the test pad being quadrilateral in shape;
- a first microbump pad that is octagonal in shape and having a first surface area that is less than a surface area of the test pad, the first microbump pad being arranged proximate to a first edge of the quadrilateral;
- wherein the test pad includes a probe mark thereon.
A test structure for performing electrical tests of devices under one or more microbumps, comprising:
- a first chip including a test pad surrounded by two or more microbump structures;
- an interposer structure spaced apart from the first chip;
- and
- wherein the two or more microbump structures extend between the first chip and the interposer structure.
1 more element
Dependencies are inferred from the claim text.