Packaged device having embedded array of components

A structure comprising:

• a first imbedded component array layer having a first array of imbedded passive devices contained therein;
• a second imbedded component array layer having a second array of imbedded passive devices contained therein;
• a first Integrated Fanout (InFO) layer residing adjacent a first surface of the first imbedded component array layer having a first plurality of traces and a second plurality of vias formed therein;
• a second InFO layer residing adjacent a first surface of the second imbedded component array layer having a second plurality of traces and a second plurality of vias formed therein;
• a connectivity layer residing adjacent a second surface of the first imbedded component array layer and adjacent a second surface of the second imbedded component array layer such that the connectivity layer is sandwiched between the first imbedded component array layer and the second imbedded component array layer, the connectivity layer a third plurality of traces and a third plurality of vias formed therein;
• a first plurality of vias passing through the first imbedded component array layer;
• and
• a second plurality of vias passing through the second imbedded component array layer.

A Printed Circuit Board (PCB) comprising:

• a core;
• an array of components formed in the core;
• a plurality of conductors coupled to the array of components;
• and
• a plurality of conductors that provide signal routing external to the PCB.

A method for constructing a Printed Circuit Board (PCB) capacitor comprising:

• forming a core having an array of components dispersed therein;
• forming a plurality of conductors coupled to the array of components;
• and
• forming a plurality of conductors that provide signal routing external to the PCB.

A Printed Circuit Board (PCB) comprising:

• a first core;
• a first array of components formed in the first core;
• a second core;
• a second array of components formed in the second core;
• a plurality of conductors coupled to the first array of components;
• a plurality of conductors coupled to the second array of components;
• and
• a plurality of conductors that provide signal routing external to the PCB.

A method for constructing a Printed Circuit Board (PCB) capacitor comprising:

• forming a first core having a first array of components dispersed therein;
• forming a second core having a second array of components dispersed therein;
• forming a plurality of conductors coupled to the first array of components;
• forming a plurality of conductors coupled to the second array of components;
• and
• forming a plurality of conductors that provide signal routing external to the PCB.