Method and apparatus for memory bandwidth reduction for small inter blocks

A video decoder for video decoding, comprising:

• processing circuitry configured to:
• receive a coded video bitstream including a current picture,
• determine whether a block size of an inter coded current block in the current picture is below a block size threshold,
• in response to a determination that the current block is below the block size threshold, determine whether the inter coded current block is associated with a fractional motion vector (MV),
• in response to a determination that the inter coded current block is associated with a fractional MV, retrieve one or more reference samples in accordance with a reference sample reduction process, and
• decode the current block based on the retrieved one or more reference samples.

A non-transitory computer readable medium having instructions stored therein, which when executed by a processor in a video decoder, causes the processor to execute a method comprising:

• receiving a coded video bitstream including a current picture;
• determining whether a block size of an inter coded current block in the current picture is below a block size threshold;
• in response to determining that the current block is below the block size threshold, determining whether the inter coded current block is associated with a fractional motion vector (MV);
• in response to determining that the inter coded current block is associated with a fractional MV, retrieving one or more reference samples in accordance with a reference sample reduction process;
• and
• decoding the current block based on the retrieved one or more reference samples.