Device with a recessed gate electrode that has high thickness uniformity

An integrated circuit comprising:

• a substrate;
• a pair of source/drain regions in the substrate;
• a gate electrode laterally between the source/drain regions, wherein a top of the gate electrode has a feature extending laterally in a closed path along a periphery of the gate electrode, wherein the feature has a first segment and a second segment respectively on opposite sides of the gate electrode, wherein the top of the gate electrode is substantially flat from the first segment to the second segment, and wherein the feature is a protrusion or a depression;
• and
• a gate dielectric layer wrapping around a bottom of the gate electrode from a sidewall of the gate electrode to a bottom surface of the gate electrode.

A method for forming a semiconductor device, the method comprising:

• forming a recess overlying a substrate;
• depositing a gate dielectric layer lining and partially filling the recess;
• depositing a multilayer film filling a remainder of the recess over the gate dielectric layer and comprising a gate electrode layer, a first sacrificial layer over the gate electrode layer, and a second sacrificial layer over the first sacrificial layer;
• performing a planarization into the second sacrificial layer that stops on the first sacrificial layer and removes the second sacrificial layer at sides of the recess;
• performing a first etch into the first and second sacrificial layers to remove the first sacrificial layer at the sides of the recess;
• and
• performing a second etch into the gate electrode layer using the first sacrificial layer as a mask to remove the gate electrode layer at the sides of the recess and to form a gate electrode underlying the first sacrificial layer in the recess.