Selectable vias for back end of line interconnects

An integrated circuit structure, comprising:

• a first layer comprising a plurality of interconnects within insulator material, the plurality of interconnects including at least a first interconnect and a second interconnect;
• a second layer above the first layer, the second layer including a plurality of selectable vias including at least a first selectable via and a second selectable via, the first selectable via comprising a first thin film transistor (TFT) structure, the second selectable via comprising a second TFT structure, wherein the first selectable via is connected to the first interconnect, and the second selectable via is connected to the second interconnect;
• and
• a third layer above the second layer, the third layer comprising a global interconnect, wherein the global interconnect is connected to both the first selectable via and the second selectable via.

An integrated circuit structure, comprising:

• a first interconnect feature;
• a second interconnect feature;
• a via structure comprising a vertically-oriented thin film transistor (TFT) structure,
• the TFT structure including
• a gate dielectric wrapped around a channel structure,
• a gate electrode wrapped around the gate dielectric,
• a source contact, and
• a drain contact,
• wherein one of the source contact or the drain contact is connected to the first interconnect feature, and the other one of the source contact or the drain contact is connected to the third interconnect, and the gate electrode is configured to receive a select signal that causes the first interconnect feature to be electrically connected to the second interconnect feature.