Management of Processor Performance Based on User Interrupts
AssigneeIntel Corporation
InventorsJacob Jun Pan, Ashok Raj, Srinivas Pandruvada
Life of this patent
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Abstract
In an embodiment, a processor for performance state adjustment includes a plurality of processing engines (PEs), a power control unit, and an input/output memory management unit (IOMMU). The IOMMU is to determine a destination PE for a user interrupt based on mapping data of the IOMMU, and to send a notification of the user interrupt to the power control unit. The notification indicates the destination PE for the user interrupt. The power control unit is to adjust a performance state of the destination PE in response to the notification of the user interrupt. Other embodiments are described and claimed.
Claims21
A method comprising:
- creating, by a processor, a task structure including a user posted interrupt descriptor associated with a user interrupt, the user posted interrupt descriptor including at least one field to indicate whether to adjust a performance state of a destination processing engine based on user interrupt notifications;
- and
- responsive to a receipt of a user interrupt notification, adjusting the performance state of the destination processing engine based on the at least one field of the user posted interrupt descriptor.
An apparatus comprising:
- a plurality of processing engines;
- and
- processing logic to:
- generate a task structure including a user posted interrupt descriptor associated with a user interrupt, the user posted interrupt descriptor including at least one field to indicate whether to adjust a performance state of a destination processing engine based on user interrupt notifications;
- and
- responsive to a receipt of a user interrupt notification, adjust the performance state of the destination processing engine based on the at least one field of the user posted interrupt descriptor.
A system comprising:
- a processor comprising a plurality of processing engines and logic to:
- generate a task structure including a user posted interrupt descriptor associated with a user interrupt, the user posted interrupt descriptor including at least one field to indicate whether to adjust a performance state of a destination processing engine based on user interrupt notifications;
- and
- responsive to a receipt of a user interrupt notification, adjust the performance state of the destination processing engine based on the at least one field of the user posted interrupt descriptor:
- and
- a system memory coupled to the processor.
Dependencies are inferred from the claim text.