Method and apparatus for generating redundant bits for error detection

A device for generating redundant bits for error detection, that are added to a block of information bits, comprising:

• a number of on-off switches that input the information bits, wherein the number is identical to a count of redundant bits calculated from a cyclic redundancy check (CRC) polynomial;
• cumulative adders configured to calculate the redundant bits by individually accumulating outputs of the number of on-off switches;
• a selector that selects one of an input information bit and the redundant bits calculated respectively by the cumulative adders to generate a data string including the information bits and the redundant bits added thereto;
• and
• a controller configure to control the on-off switches and the selector using a permutation pattern determined based on the CRC polynomial.

A method for generating redundant bits for error detection, that are added to a block of information bits, comprising:

• by a number of on-off switches, inputting the information bits and passing or blocking an information bit according to a first control signal, wherein the number is identical to a count of redundant bits calculated from a cyclic redundancy check (CRC) polynomial;
• by cumulative adders calculating the redundant bits by individually accumulating outputs of the number of on-off switches;
• by a selector, selecting one of an input information bit and the redundant bits calculated respectively by the cumulative adders to generate a data string including the information bits and the redundant bits added thereto, according to a second control signal;
• and
• by a controller, outputting the first control signal and the second control signal for controlling the on-off switches and the selector using a permutation pattern determined based on the CRC polynomial.

A device for detecting errors using redundant bits enabling error detection, that are added to a block of information bits, comprising:

• a number of on-off switches that input the information bits, wherein the number is identical to a count of redundant bits calculated from a cyclic redundancy check (CRC) polynomial;
• cumulative adders that calculate the redundant bits by individually accumulating outputs of the number of on-off switches;
• a selector that selects one of an input information bit and the redundant bits calculated respectively by the cumulative adders to generate a data string including the information bits and the redundant bits added thereto;
• a controller that controls the on-off switch means and the selection means using a permutation pattern determined based on the CRC polynomial;
• and
• a decision unit configured to decide whether an error exists or not, by comparing a redundant bit of the received data to a redundant bit calculated.

A non-transitory recording medium storing a program for functioning a computer as a device for generating redundant bits for error detection, that are added to a block of information bits, the program comprising:

• by a number of on-off switches, inputting the information bits, wherein the number is identical to a count of redundant bits calculated from a cyclic redundancy check (CRC) polynomial;
• by cumulative adders, calculating the redundant bits by individually accumulating outputs of the number of on-off switches;
• by a selector, selecting one of an input information bit and the redundant bits calculated respectively by the cumulative adders, to generate a data string including the information bits and the redundant bits added thereto;
• and
• by a controller, controlling the on-off switches and the selector using a permutation pattern determined based on the CRC polynomial.

A non-transitory recording medium storing a program for detecting errors using redundant bits enabling error detection, that are added to a block of information bits, the program comprising:

• by a number of on-off switches, inputting the information bits, wherein the number is identical to a count of redundant bits calculated from a cyclic redundancy check (CRC) polynomial;
• by cumulative adders, calculating the redundant bits by individually accumulating outputs of the number of on-off switches;
• by a selector, selecting one of an input information bit and the redundant bits calculated respectively by the cumulative adders, to generate a data string including the information bits and the redundant bits added thereto;
• by a controller, controlling the on-off switches and the selector using a permutation pattern determined based on the CRC polynomial;
• and
• by a decision unit, deciding on whether an error exists or not, by comparing a redundant bit of the received data to a redundant bit calculated.