# US 2020/0110714 A1 · Dynamically configuring transmission lines of a bus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2020/0110714 A1 - Document ID: US20200110714A1 - Status: Published application - Kind: A1 - Application number: 16/579,515 - Filed: 2019-09-23 - Published: 2020-04-09 - Earliest claimed: 2018-10-05 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Michael Dieter Richter; Thomas Hein; Martin Brox; Peter Mayer; Wolfgang Anton Spirkl - Web page: https://patentgrep.com/patent/US20200110714A1 ## CPC - G06F 13/1668: {Details of memory controller} - G06F 3/0607: {by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device} - G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - G06F 13/1678: {using bus width} - G06F 13/40: Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} - G06F 13/4243: {with synchronous protocol} - G11C 7/1045: {Read-write mode select circuits} - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G06F 2213/0056: Use of address and non-data lines as data lines for specific data transfers to temporarily enlarge the data bus and increase information transfer rate - G11C 5/066: {Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals} - G11C 7/1018: {Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters} - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods, systems, and devices for dynamically configuring transmission lines of a bus between two electronic devices (e.g., a controller and memory device) are described. A first device may determine a quantity of bits (e.g., data bits, control bits) to be communicated with a second device over a data bus. The first device may partition the data bus into a first set of transmission lines (e.g., based on the quantity of data bits) and a second set of transmission lines (e.g., based on the quantity of control bits). The first device may communicate the quantity of data bits over the first set of transmission lines and communicate the quantity of control bits over the second set of transmission lines. In some cases, the first device may repartition the data bus based on different quantities of data bits and control bits to be communicated with the second device at a different time. ## Claims ### Claim 1 A method, comprising: determining, by a host device, a quantity of data bits and a quantity of control bits associated with a memory device, the host device and the memory device coupled with a data bus comprising transmission lines; selecting, from the data bus, a first set of the transmission lines based at least in part on the quantity of data bits and a second set of the transmission lines based at least in part on the quantity of control bits; transferring, over the first set of the transmission lines, the quantity of data bits to the memory device; and transferring, over the second set of the transmission lines, the quantity of control bits between the host device and the memory device. ### Claim 2 (depends on 1) The method of claim 1, wherein the quantity of control bits comprises a first quantity of control bits and the quantity of data bits comprises a first quantity of data bits, the method further comprising: determining a second quantity of data bits and a second quantity of control bits associated with the memory device; and switching at least one transmission line from one of the first or second sets of transmission lines to the other set based at least in part on the second quantity of data and control bits. ### Claim 3 (depends on 1) The method of claim 1, wherein the quantity of control bits comprises a command for a memory operation, the method further comprising: determining a timing parameter associated with the command, wherein selecting the first and second sets of transmission lines is based at least in part on the timing parameter. ### Claim 4 (depends on 1) The method of claim 1, further comprising: transferring the quantity of control bits and the quantity of data bits at a same data rate. ### Claim 5 (depends on 1) The method of claim 1, further comprising: transferring a command for a memory operation, an address indicating a memory location targeted for the memory operation, and error detection bits corresponding to the command and the address. ### Claim 6 (depends on 5) The method of claim 5, wherein the command comprises an access command, the method further comprising: modifying, relative to a previous access command and based at least in part on the quantity of control bits, a quantity of memory cells to be accessed in response to the access command. ### Claim 7 (depends on 1) The method of claim 1, further comprising: selecting the quantity of data bits based at least in part on the quantity of control bits; and sending an indication of the quantity of data bits to the memory device. ### Claim 8 (depends on 1) The method of claim 1, wherein the quantity of data bits comprises a first quantity of data bits, the method further comprising: determining that a second quantity of data bits associated with the memory device is different than the first quantity of data bits; and adjusting the data bus by adding or removing one or more transmission lines from the data bus based at least in part on determining the second quantity of data bits. ### Claim 9 (depends on 8) The method of claim 8, further comprising: transmitting an indication of the adjusted data bus over the second set of the transmission lines. ### Claim 10 (depends on 1) The method of claim 1, further comprising: modulating the quantity of control bits and the quantity of data bits according to a modulation scheme that includes three or more voltage levels. ### Claim 11 A method, comprising: determining, by a memory device, that a data bus comprising transmission lines has been divided into a first set of transmission lines for control content and a second set of transmission lines for data content; communicating a first set of control bits over the first set of transmission lines and a first set of data bits over the second set of transmission lines; determining that the data bus has been divided into a third set of transmission lines for control content and a fourth set of transmission lines for data content, the division of the third and fourth sets of transmission lines being different than the first and second sets of transmission lines; and communicating, a second set of control bits over the third set of transmission lines and a second set of data bits over the fourth set of transmission lines. ### Claim 12 (depends on 11) The method of claim 11, further comprising: receiving, over the third set of transmission lines, a set of error detection bits included in the second set of control bits; and determining that the second set of control bits comprises an error based at least in part on the set of error detection bits. ### Claim 13 (depends on 12) The method of claim 12, further comprising: transmitting an indication of the error to a memory controller coupled with the data bus. ### Claim 14 (depends on 12) The method of claim 12, further comprising: refraining, based at least in part on determining the error, from complying with additional commands for memory operations until receiving an indication from a memory controller coupled with the data bus. ### Claim 15 (depends on 11) The method of claim 11, further comprising, receiving a command that changes a quantity of memory cells to be read or written in response to an access command from a first quantity to a second quantity; and reading or writing a set of memory cells corresponding to the second quantity in response to the access command included in the first set of control bits. ### Claim 16 (depends on 11) The method of claim 11, further comprising: receiving, after communicating the second set of control bits and the second set of data bits, an indication that a quantity of transmission lines included in the data bus has changed; and determining that the data bus has been divided into a fifth set of transmission lines associated with control content and a sixth set of transmission lines associated with data content. ### Claim 17 (depends on 16) The method of claim 16, further comprising: communicating a third set of control bits over the fifth set of transmission lines and a fourth set of data bits over the sixth set of transmission lines. ### Claim 18 An apparatus, comprising: nodes configured to communicate with a memory device via transmission lines; and a memory controller coupled with the nodes and operable to: divide the nodes into a first set of nodes and a second set of nodes; transmit a first set of control bits to the memory device via the first set of nodes and exchange a first set of data bits with the memory device via the second set of nodes; divide the nodes into a third set of nodes and a fourth set of nodes different than the first and second sets of nodes; and transmit a second set of control bits to the memory device via the third set of nodes and exchange a second set of data bits with the memory device via the fourth set of nodes. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the memory controller is further operable to: determine a quantity of the first set of control bits and a quantity of the first set of data bits, wherein dividing the nodes into the first and second sets of nodes is based at least in part on the quantity of the first set of control bits and the quantity of the first set of data bits. ### Claim 20 (depends on 18) The apparatus of claim 18, wherein the third set of nodes comprises the first set of nodes plus at least one node, and wherein the fourth set of nodes comprises the second set of nodes minus the at least one node. ### Claim 21 An apparatus, comprising: transmission lines configured as a data bus; and a memory device coupled with the transmission lines and operable to: determine that the data bus has been divided into a first set of transmission lines and a second set of transmission lines; receive a first set of control bits from a memory controller over the first set of transmission lines and exchange a first set of data bits with the memory controller over the second set of transmission lines; determine that a transmission line has been switched from the first set of transmission lines to the second set of transmission lines; and exchange a second set of data bits with the memory controller over the transmission line switched to the second set of transmission lines. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the memory device is operable to: receive a second set of control bits from the memory controller over transmission lines of the first set of transmission lines other than the transmission line switched to the second set of transmission lines. ### Claim 23 (depends on 21) The apparatus of claim 21, wherein the memory device is operable to: receive, from the memory controller, an indication of the first and second sets of transmission lines, wherein the determination that the data bus has been divided into the first and second sets of transmission lines is based at least in part on the indication. ### Claim 24 (depends on 21) The apparatus of claim 21, wherein the memory device is operable to: receive, from the memory controller, an indication that the transmission line has been switched, wherein the determination that the transmission line has been switched is based at least in part on the indication.