Energy-filtered cold electron devices and methods
AssigneeBoard of Regents, The University of Texas System
InventorsSeong Jin KOH, Pradeep BHADRACHALAM, Liang-Chieh MA
Life of this patent
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Abstract
Energy-filtered cold electron devices use electron energy littering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.
Claims20
1-131. (canceled)
A method for forming an energy-filtered cold electron transistor comprising the steps of:
- providing a substrate;
- forming or depositing an isolation layer on the substrate;
- forming or depositing a semiconductor material or a metal on the isolation layer;
- forming or depositing a sacrificial material on the semiconductor material or the metal;
- forming a central island by etching or removing the sacrificial material and the semiconductor material or the metal around the central island;
- forming or depositing a second tunneling barrier material around the semiconductor material or the metal of the central island, wherein the second tunneling barrier material forms a second tunneling barrier on a first side of the central island and an additional second tunneling barrier on a second side of the central island;
- forming or depositing a first tunneling barrier material on top and around the sacrificial material on the central island, on the second tunneling barrier, and on the isolation layer, wherein the first tunneling barrier material forms a first tunneling barrier adjacent to the second tunneling barrier and an additional first tunneling barrier adjacent to the additional second tunneling barrier;
- forming or depositing an electrode material on the first tunneling barrier to form a first electrode adjacent to the first tunneling barrier and a second electrode adjacent to the additional first tunneling barrier;
- removing or lifting off all materials above a plane substantially level with a top of the first electrode and the second electrode;
- forming or depositing a gate dielectric above the central island;
- and
- forming or depositing a gate electrode on the gate dielectric.
Dependencies are inferred from the claim text.