Uplink power allocation method, uplink power allocation device and uplink power allocation system

An uplink power control device, comprising a processor, a memory and a transceiver, wherein the processor is configured to read a program stored in the memory to:

• determine users to be paired, based on locations of the users within the cell;
• determine Patten Division Multiple Access (PDMA) pattern matrixes, allocate different PDMA pattern vector groups for the users respectively, and obtain a power control pattern matrix based on the PDMA pattern vector groups;
• and
• determine power control factors of the users, and determine an uplink transmission power of each user:
• the transceiver is configured to receive and transmit data;
• the processor is configured to manage a bus architecture and perform a general processing;
• and
• the memory is configured to store data for the operation of the processor.

An uplink power allocation system, comprising a base station and a receiver, wherein the base station comprises an uplink power allocation device, the uplink power allocation device comprises a processor, a memory and a transceiver, wherein the processor is configured to read a program stored in the memory to:

• determine different kinds of users to be paired, based on locations of the users within the cell;
• determine Patten Division Multiple Access (PDMA) pattern matrixes, allocate different PDMA pattern vector groups for the users respectively, and obtain a power control pattern matrix based on the PDMA pattern vector groups;
• and
• determine power control factors of the users, and determine an uplink transmission power of each user;
• the transceiver is configured to receive and transmit data;
• the processor is configured to manage a bus architecture and perform a general processing:
• and
• the memory is configured to store data for the operation of the processor;
• wherein the receiver comprises a processor, a memory and a transceiver, wherein the processor is configured to read a program stored in the memory to cancel the users demodulated correctly through a successive interference cancellation and detect the other users;
• the transceiver is configured to receive and transmit data;
• the processor is configured to manage a bus architecture and perform a general processing:
• and
• the memory is configured to store data for the operation of the processor.