Image processing apparatus, image processing method, and image processing program
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsRyuji HADA, Atsushi MASUDA
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Abstract
An image processing apparatus includes first and second line buffers, an image processing circuit configured to perform an image processing on first pixel data stored in the first line buffer and then second pixel data stored in the second line buffer, and a controller configured to control writing of the second pixel data in the second line buffer at a timing aligned with a synchronizing signal and reading of the second pixel data written in the second line buffer for the image processing by the image processing circuit at a timing of a completion of the image processing by the image processing circuit of the first pixel data stored in the first line buffer.
Claims20
An image processing apparatus comprising:
- first and second line buffers;
- an image processing circuit configured to perform an image processing on first pixel data stored in the first line buffer and then second pixel data stored in the second line buffer;
- and
- a controller configured to control writing of the second pixel data in the second line buffer at a timing aligned with a synchronizing signal and reading of the second pixel data written in the second line buffer for the image processing by the image processing circuit at a timing of a completion of the image processing by the image processing circuit of the first pixel data stored in the first line buffer.
An image processing apparatus comprising:
- first, second, and third line buffers;
- an image processing circuit configured to perform an image processing on first pixel data stored in the first line buffer and then second pixel data stored in the second line buffer;
- and
- a controller configured to control writing of third pixel data into the first line buffer if the image processing circuit completes the image processing on the first pixel data stored in the first line buffer within a period of the synchronizing signal, and into the third line buffer if a time period for the image processing by the image processing circuit of the first pixel data stored in the first line buffer is longer than a period of the synchronizing signal.
A method performed by an image processing apparatus, the method comprising:
- writing first pixel data into a first line buffer at a timing aligned with a synchronizing signal;
- reading the first pixel data stored in the first line buffer for an image processing performed by an image processing circuit while writing second pixel data into a second line buffer at a timing aligned with the synchronizing signal;
- and
- reading the second pixel data stored in the second line buffer for the image processing at a timing of a completion of the image processing of the first pixel data stored in the first line buffer.
Dependencies are inferred from the claim text.