Back to results
US 2020/0092100 A1Published application
Authentication apparatus
AssigneesKabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
InventorsMasahiro Kimura, Yoshinari Ojima
Life of this patent
Estimating the term…
Abstract
An authentication apparatus of embodiments has a counter circuit and a pseudo-pass generating circuit. The counter circuit counts the number of times an inputted cryptographic key and a cryptographic key set in advance consecutively do not match. The pseudo-pass generating circuit outputs a pseudo-pass response when the number of times the keys consecutively do not match, which is counted by the counter circuit, exceeds a predetermined value.
Claims6
An authentication apparatus comprising:
- a counter circuit configured to count a number of times an inputted cryptographic key and a cryptographic key set in advance consecutively do not match;
- and
- a pseudo-pass generating circuit configured to output a pseudo-pass response when the number of times the keys consecutively do not match, which is counted by the counter circuit, exceeds a predetermined value.
Dependencies are inferred from the claim text.