Encoder, associated encoding method and flash memory controller

A flash memory controller, arranged to access a flash memory module and comprising:

• a memory, arranged to store a code;
• a microprocessor, arranged to execute the code in order to control access of the flash memory module;
• and
• an encoder, arranged to encode the data blocks in order to obtain a plurality of parity blocks, wherein the encoder comprises:
• a first barrel shifter module, arranged to perform operations upon a plurality of data blocks in order to generate a plurality of partial parity blocks, wherein the partial parity blocks comprise a first portion of partial parity blocks and a second portion of partial parity blocks;
• a first computing circuit, coupled to the second portion of partial parity blocks, arranged to generate a first calculating result according to the output of the second portion of partial parity blocks;
• an adjusting circuit, arranged to adjust the first portion of partial parity blocks by adding the first portion of partial parity blocks on the first calculating result to generate an adjusted first portion of partial parity blocks;
• a first circulant convolution computing circuit, coupled to the adjusting circuit, and arranged to perform circulant convolution operations upon the adjusted first portion of partial parity blocks, in order to generate a first portion of parity blocks;
• and
• a second computing circuit, coupled to the first circulant convolution computing circuit and the first computing circuit, the second computing circuit arranged to generate a second portion of parity blocks by adding the first portion of parity blocks on the first calculating result;
• wherein the first portion of parity blocks and the second portion of parity blocks serve as a plurality of parity blocks generated by the encoder for the data blocks.

An encoding method for a flash memory controller, comprising:

• processing a plurality of data blocks to generate a plurality of partial parity blocks, wherein the partial parity blocks comprise a first portion of partial parity blocks and a second portion of partial parity blocks;
• using a first computing circuit to generate a first calculating result according to the second portion of partial parity blocks;
• adjusting the first portion of partial parity blocks by adding the first portion of partial parity blocks on the first calculating result, in order to generate an adjusted first portion of partial parity blocks;
• performing circulant convolution operations upon the adjusted first portion of partial parity blocks, in order to generate a first portion of parity blocks;
• and
• using a second computing circuit to generate a second portion of parity blocks by adding the first portion of parity blocks on the first calculating result;
• wherein the first portion of parity blocks and the second portion of parity blocks serve as a plurality of parity blocks generated by encoding the data blocks, and the data blocks and the parity blocks are written into a flash memory.

An encoder installed in a flash memory controller, comprising:

• a barrel shifter module, arranged to perform operations upon a plurality of data blocks in order to generate a plurality of partial parity blocks, wherein the partial parity blocks comprise a first portion of partial parity blocks and a second portion of partial parity blocks;
• an adjusting circuit, arranged to adjust the first portion of partial parity blocks according to the second portion of partial parity blocks, in order to generate an adjusted first portion of partial parity blocks;
• a circulant convolution computing circuit, coupled to the adjusting circuit, and arranged to perform circulant convolution operations on the adjusted first portion in order to generate a first portion of parity blocks;
• and
• a computing circuit, coupled to the circulant convolution computing circuit, the computing circuit arranged to generate a second portion of parity blocks at least according to the first portion of parity blocks;
• wherein the first portion of parity blocks and the second portion of parity blocks serve as a plurality of parity blocks generated by the encoder for the data blocks, and the data blocks and the parity blocks are written into a flash memory.