Methods and systems for transcoder, fec and interleaver optimization
AssigneeAvago Technologies International Sales Pte. Limited
InventorsChungming Tu, Thomas V. Souvignier, Ahmad Darabiha
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Abstract
An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.
Claims20
An interleaved encoder comprising:
- a plurality of encoders including L parallel encoders;
- and
- a first switch circuit configured to sequentially couple an input node to an input port of one of the plurality of encoders,
- wherein:
- the input node is configured to receive a group of K*L symbols,
- each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses, and
- the first switch circuit is synched with clock pulses of the group of K*L clock pulses, and is configured to sequentially couple the input node to an input port of a subsequent one of the plurality of encoders in response to each clock pulse of the group of K*L clock pulses.
A system comprising:
- an input node disposed to receive a group of symbols;
- a plurality of encoders disposed in parallel;
- an input switch circuit configured to sequentially couple an input port of one of the plurality of encoders to the input node;
- an output switch circuit in synch with the input switch circuit;
- and
- an output node disposed to provide an interleaved output code,
- wherein:
- each symbol of the group of symbols is received in synch with a respective clock pulse of a group of clock pulses,
- the input switch circuit is synched with clock pulses of the group of clock pulses.
An electronic device comprising:
- an interleaved encoder configured to generate an interleaved output code, the interleaved encoder comprising:
- an input node configured to receive a group of symbols;
- a plurality of RS encoders disposed in parallel;
- and
- a first switch circuit configured to sequentially couple the input node to an input port of one of the plurality of RS encoders,
- wherein:
- each symbol of the group of symbols is received in synch with a respective clock pulse of a group of clock pulses, and
- the first switch circuit is synched with clock pulses of the group of clock pulses, and is configured to sequentially couple the input node to an input port of a subsequent one of the plurality of RS encoders in response to each clock pulse of the group of clock pulses.
Dependencies are inferred from the claim text.