Successive approximation register analog-to-digital converter and control circuit thereof

A control circuit of a successive approximation register analog-to-digital converter (SAR ADC) comprising a comparator and a switched-capacitor digital-to-analog converter (DAC), the switched-capacitor DAC comprising a capacitor and a driving circuit that is electrically connected to the capacitor, the driving circuit comprising a first P-type MOSFET and a first N-type MOSFET, and a gate of the first P-type MOSFET being not electrically connected to a gate of the first N-type MOSFET, the control circuit comprising:

• a memory configured to store an output value of the comparator;
• a first inverter, coupled between the memory and the first P-type MOSFET and configured to generate a first control signal for controlling the first P-type MOSFET, comprising:
• a second P-type MOSFET having a first aspect ratio;
• and
• a second N-type MOSFET having a second aspect ratio;
• and
• a second inverter, coupled between the memory and the first N-type MOSFET and configured to generate a second control signal for controlling the first N-type MOSFET, comprising:
• a third P-type MOSFET having a third aspect ratio;
• and
• a third N-type MOSFET having a fourth aspect ratio;
• wherein the first aspect ratio is greater than the second aspect ratio and/or the third aspect ratio is smaller than the fourth aspect ratio.

A control circuit of a successive approximation register analog-to-digital converter (SAR ADC) comprising a comparator and a switched-capacitor digital-to-analog converter (DAC), the switched-capacitor DAC comprising a capacitor and a driving circuit that is electrically connected to the capacitor, the driving circuit comprising a P-type MOSFET and a N-type MOSFET, and a gate of the P-type MOSFET being not electrically connected to a gate of the N-type MOSFET, the control circuit comprising:

• a first memory coupled to the comparator and configured to store an output value of the comparator;
• a second memory coupled to the comparator and configured to store the output value of the comparator;
• a first buffer having a first delay, coupled between the first memory and the P-type MOSFET, and configured to generate a first control signal;
• and
• a second buffer having a second delay, coupled between the second memory and the N-type MOSFET, and configured to generate a second control signal;
• wherein the P-type MOSFET is controlled by the first control signal, the N-type MOSFET is controlled by the second control signal, and the second delay is greater than the first delay.