Highspeed/low power symbol compare
AssigneeMicrosoft Technology Licensing, LLC
InventorsRyan S. HARADEN, Shankar S. NARAYAN
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.
Claims21
1-20. (canceled)
An integrated circuit, comprising:
- a first plurality of compare lanes, and
- a second plurality of compare lanes;
- wherein each of the first plurality of compare lanes is configured to:
- receive a first plurality of settings bits indicating a first programmable criteria for the compare lane, the first programmable criteria indicating at least one of a first programmable value or a first configurable comparison type,
- receive a first input symbol,
- determine, during a first processing cycle of the integrated circuit, a first comparison result for the first input symbol based on the first programmable criteria, and
- output the first comparison result for the first input symbol to a downstream compare lane of the second plurality of compare lanes, wherein the downstream compare lane is configured to use the first input symbol and the first comparison result for the first input symbol as inputs during a second processing cycle of the integrated circuit subsequent to the first processing cycle.
A method for use with an integrated circuit, the method comprising:
- at each of a first plurality of compare lanes of the integrated circuit:
- receiving a first plurality of settings bits indicating a first programmable criteria for the compare lane, the first programmable criteria indicating at least one of a first programmable value or a first configurable comparison type,
- receiving a first input symbol,
- determining, during a first processing cycle of the integrated circuit, a first comparison result for the first input symbol based on the first programmable criteria, and
- outputting the first comparison result for the first input symbol to a downstream compare lane included in a second plurality of compare lanes of the integrated circuit, wherein the downstream compare lane is configured to use the first input symbol and the first comparison result for the first input symbol as inputs during a second processing cycle of the integrated circuit subsequent to the first processing cycle.
An integrated circuit, comprising:
- a first plurality of compare lanes, and
- a second plurality of compare lanes;
- wherein each of the first plurality of compare lanes is configured to:
- receive a first plurality of settings bits indicating a first programmable criteria for the compare lane, the first programmable criteria indicating at least one of a first programmable value or a first configurable comparison type;
- receive a first input symbol;
- and
- during a first processing cycle of the integrated circuit:
- determine a first comparison result for the first input symbol based on the first programmable criteria;
- output the first comparison result for the first input symbol to a downstream compare lane of the second plurality of compare lanes;
- and
- output the first comparison result for the first input symbol to a first feature counter shared by each of the first plurality of compare lanes;
- and
- wherein the downstream compare lane of the second plurality of compare lanes is configured to:
- receive a second plurality of settings bits indicating a second programmable criteria for the compare lane, the second programmable criteria indicating at least one of a second programmable value or a second configurable comparison type;
- and
- during a second processing cycle of the integrated circuit subsequent to the first processing cycle:
- determine an additional comparison result for the first input symbol based on the second programmable criteria;
- and
- output the additional comparison result to a second feature counter shared by each of the second plurality of compare lanes.
Dependencies are inferred from the claim text.