US 2020/0091913 A1Published application

Semiconductor device

AssigneeToshiba Memory Corporation

InventorNaoaki KANAGAWA

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Abstract

A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

Claims20

Dependent claims

A semiconductor device comprising:

a first node;
a second node;
first, second, and third semiconductor regions, each of which is surrounded by an isolation layer;
first and second transistors of a first conductivity type connected in parallel between the first node and the second node, and provided within the first semiconductor region;
a third transistor of the first conductivity type connected between the second node and the first transistor, and provided within the second semiconductor region;
and
a fourth transistor of the first conductivity type connected between the second node and the second transistor, and provided within the third semiconductor region, wherein
gate electrodes of the first and second transistors extend in a first direction and are spaced from each other in a second direction that is perpendicular to the first direction, and gate electrodes of the third and fourth transistors also extend in the first direction, and
a first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.

6 more elements

A NOR gate circuit comprising:

an output node;
a power supply node;
first, second, and third generally rectangular semiconductor regions, each of which is surrounded by an isolation layer;
first and second transistors of a P conductivity type connected in parallel between the output node and the power supply node, and formed within the first semiconductor region so that drain/source regions thereof are aligned in a first direction;
a third transistor of the P conductivity type connected between the power supply node and the first transistor, and formed within the second semiconductor region so that drain/source regions thereof are aligned in the first direction;
and
a fourth transistor of the P conductivity type connected between the power supply node and the second transistor, and provided within the third semiconductor region so that drain/source regions thereof are aligned in the first direction, wherein
gate electrodes of the first, second, third, and fourth transistors extend in a second direction that is perpendicular to the first direction, and
a first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the first direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the first direction.

6 more elements

A NAND gate circuit comprising:

a reference node;
an output node;
first, second, and third generally rectangular semiconductor regions, each of which is surrounded by an isolation layer;
first and second transistors of an N conductivity type connected in parallel between the reference node and the output node, and formed within the first semiconductor region so that drain/source regions thereof are aligned in a first direction;
a third transistor of the N conductivity type connected between the output node and the first transistor, and formed within the second semiconductor region so that drain/source regions thereof are aligned in the first direction;
and
a fourth transistor of the N conductivity type connected between the output node and the second transistor, and provided within the third semiconductor region so that drain/source regions thereof are aligned in the first direction, wherein
gate electrodes of the first, second, third, and fourth transistors extend in a second direction that is perpendicular to the first direction, and
a first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the first direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the first direction.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/286,528Filed 26 Feb 2019
Priority: JP 2018-17199614 Sep 2018
Published: 19 Mar 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03K 19/09441
Using MOSFET or insulated gate field-effect transistors, i.e. IGFET: of the same canal type
H03K 19/20
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: characterised by logic function, e.g. AND, OR, NOR, NOT…
H10D 84/0151
The components including insulated gates, e.g. IGFETs: manufacturing their isolation regions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe