Electronic circuit
AssigneeKabushiki Kaisha Toshiba
InventorShusuke KAWAI
Life of this patent
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Abstract
According to one embodiment, an electronic circuit includes a plurality of first transistors, a control circuit, a sample hold circuit and a calculation circuit. The control circuit selectively performs a first operation and a second operation, the first operation supplying a driving control signal to a gate terminal of a semiconductor switching element using the plurality of first transistors, and the second operation supplying a pulse current for measurement to the gate terminal using part of the plurality of first transistors. The sample hold circuit samples a voltage of the gate terminal during a period in which the pulse current is supplied to the gate terminal in the second operation. The calculation circuit calculates a gate resistance of the semiconductor switching element based on the sampled voltage.
Claims17
An electronic circuit, comprising:
- a plurality of first transistors;
- a control circuit configured to selectively perform a first operation and a second operation,
- the first operation supplying a driving control signal to a gate terminal of a semiconductor switching element using the plurality of first transistors, and
- the second operation supplying a pulse current for measurement to the gate terminal using part of the plurality of first transistors;
- a sample hold circuit configured to sample a voltage of the gate terminal during a period in which the pulse current is supplied to the gate terminal in the second operation;
- and
- a calculation circuit configured to calculate a gate resistance of the semiconductor switching element based on the sampled voltage.
An electronic circuit, comprising:
- a plurality of first transistors;
- a plurality of second transistors connected to the plurality of first transistors in series, respectively, connection nodes between the plurality of first transistors and the plurality of second transistors being electrically connected to a gate terminal of a semiconductor switching element;
- a control circuit configured to control the first transistors and the second transistors,
- the control circuit supplying a pulse current for measurement to the gate terminal of the semiconductor switching element through at least one of the plurality of first transistors and
- the control circuit discharging a charge accumulated in a parasitic capacitor of the semiconductor switching element due to the pulse current through at least one of the plurality of second transistors;
- a sample hold circuit configured to sample a voltage of the gate terminal during a discharge period of the charge;
- and
- a calculation circuit configured to calculate a gate resistance of the semiconductor switching element based on the sampled voltage.
Dependencies are inferred from the claim text.