Glitch-free clock generator and method for generating glitch-free clock signal

A method for generating a glitch-free clock signal, comprising:

• generating, by a clock generating circuit, an internal clock signal;
• receiving, by a first filter circuit, the internal clock signal and an enable signal;
• generating, by the first filter circuit, a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the clock signal;
• receiving, by a second filter circuit, the first filtered enable signal;
• generating, by the second filter circuit, a second filtered enable signal in response to the first filtered enable signal;
• providing, by the second filter circuit, a delayed signal that is a delayed version of the second filtered enable signal;
• receiving, by an output gate, the internal clock signal and the second filtered enable signal;
• and
• providing, by the output gate, the glitch-free clock signal based on a first logic operation of the internal clock signal and the second filtered enable signal.

A clock generator for generating an output clock signal in response to an enable signal, comprising:

• a clock generating circuit that generates an internal clock signal;
• a first filter circuit that receives the internal clock signal and the enable signal, and generates a first filtered enable signal indicative of a first validity of the enable signal;
• a second filter circuit that receives the first filtered enable signal and generates a second filtered enable signal, wherein the second filter circuit applies a delay on the second filtered enable signal to generate a delayed signal, wherein the clock generating circuit operates in response to the second filtered enable signal and the delayed signal;
• and
• an output gate that receives the second filtered enable signal and the internal clock signal, and generates the output clock signal.