System and method for reducing current noise in a vco and buffer
AssigneeQUALCOMM Incorporated
InventorsYue CHAO, Yinghan WANG, Marco ZANUSO, Rajagopalan RANGARAJAN
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Abstract
A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.
Claims25
A voltage controlled oscillator (VCO) and buffer circuit, comprising:
- a voltage controlled oscillator (VCO);
- a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs);
- and
- a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.
A method for reducing noise in a voltage controlled oscillator (VCO) and buffer, comprising:
- generating a signal using a voltage controlled oscillator (VCO);
- receiving the signal in a buffer circuit, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs);
- and
- compensating the parasitic gate-source capacitance (Cgs) of the first transistor using a second transistor coupled across the first transistor, the second transistor having a parasitic gate-source capacitance (Cgs) and a parasitic gate-drain capacitance (Cgd), the parasitic gate-source capacitance (Cgs) and the parasitic gate-drain capacitance (Cgd) of the second transistor compensating for a non-linearity of the parasitic gate-source capacitance (Cgs) of the first transistor.
A device, comprising:
- voltage controlled oscillator (VCO) means for generating a signal;
- means for buffering an output of the VCO means, the means for buffering comprising a first transistor having a parasitic gate-source capacitance (Cgs);
- and
- means for compensating for a non-linearity of the parasitic gate-source capacitance (Cgs) of the first transistor.
A phase locked loop (PLL) circuit, comprising:
- a phase/frequency detector configured to provide an error signal;
- a charge pump responsive to the error signal, the charge pump configured to provide a control signal;
- a filter configured to receive the control signal and provide a filtered voltage signal;
- a voltage controlled oscillator (VCO) configured to receive the filtered voltage signal, the VCO having a buffer circuit, the buffer circuit comprising:
- a first transistor having a parasitic gate-source capacitance (Cgs);
- a second transistor coupled across the first transistor, the second transistor having a parasitic gate-source capacitance (Cgs) and a parasitic gate-drain capacitance (Cgd), the parasitic gate-source capacitance (Cgs) and the parasitic gate-drain capacitance (Cgd) of the second transistor configured to compensate for a non-linearity of the parasitic gate-source capacitance (Cgs) of the first transistor;
- and
- a feedback circuit configured to divide an output of the VCO by a factor, N, and provide the divided VCO output to the phase/frequency detector.
Dependencies are inferred from the claim text.