US 2020/0091713 A1 · SINGLE EVENT LATCH-UP (SEL) MITIGATION DETECT AND MITIGATION

Abstract

An integrated circuit (IC) chip having circuitry adapted to detect and unlatch a latched transistor, and methods for operating the same are provided. In one example, an IC chip includes a body, a power rail disposed in the body and coupled to at least one of a plurality of contract pads disposed on the body, and a first core circuit disposed in the body. The first core circuit includes a first current limiting circuit, a silicon controlled rectifier (SCR) device having a first transistor, a second transistor, and a first latch sensing circuit. The first current limiting circuit is coupled to the power rail. First terminals of the first and second transistors are coupled to the first current limiting circuit. The first latch sensing circuit has a first input terminal coupled to second terminals of the first and second transistors. The first latch sensing circuit also has an output terminal coupled to the first current limiting circuit.

Claims20

Dependent claims

An integrated circuit (IC) chip, comprising:

a body having a plurality of contract pads:
a power rail disposed in the body and coupled to at least one of the plurality of contract pads;
and
a first core circuit disposed in the body, the first core circuit comprising:
a first current limiting circuit coupled to the power rail;
a silicon controlled rectifier (SCR) device including a first transistor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the first current limiting circuit;
a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the first current limiting circuit;
and
a first latch sensing circuit having a first input terminal coupled to the second terminals of the first and second transistors, the first latch sensing circuit having an output terminal coupled to the first current limiting circuit.

6 more elements

An integrated circuit (IC) chip, comprising:

a body having a plurality of contract pads:
a power rail disposed in the body and coupled to at least one of the plurality of contract pads;
a silicon controlled rectifier (SCR) device having a first transistor disposed in the body, the first transistor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the power rail;
a second transistor disposed in the body and having a first terminal and a second terminal, the first terminal of the second transistor coupled to the power rail;
a first latch sensing circuit configured to output a first signal in response to the SCR device operating in an unlatched state, and to output a second signal in response to the SCR device operating in a latched state;
and
a first current limiting circuit coupling the first and second transistors to the power rail, the first current limiting circuit configured to reduce current passing from the power rail to the SCR device in response to a signal being received from the first latch sensing circuit switching from the first signal to the second signal.

4 more elements

Dependencies are inferred from the claim text.

Single event latch-up (sel) mitigation detect and mitigation

Life of this patent

Single event latch-up (sel) mitigation detect and mitigation

Life of this patent

Abstract

Claims20