Circuit and method for protecting a voltage regulating circuit against electrostatic discharges
AssigneeSTMicroelectronics (Rousset) SAS
InventorNicolas Demange
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.
Claims20
An integrated circuit, comprising:
- a first terminal and a second terminal configured to be coupled to respective antenna terminals;
- a first transistor having a first conduction terminal connected to the first terminal, a second conduction terminal connected to the second terminal, and a control terminal;
- a rectification circuit having first and second inputs coupled to the first and second terminals, respectively, and having first and second outputs;
- an electrostatic discharge (ESD) detection circuit configured to sense an ESD event at said first output of the rectification circuit and in response thereto assert a control signal;
- and
- a control circuit configured to selectively connect the control terminal of the first transistor to one of the first and second terminals in response to assertion of the control signal.
An integrated circuit, comprising:
- a first terminal and a second terminal configured to be coupled to respective antenna terminals;
- a first transistor having a first conduction terminal connected to the first terminal, a second conduction terminal connected to the second terminal, and a control terminal;
- a rectification circuit having first and second inputs coupled to the first and second terminals, respectively, and having first and second outputs;
- an electrostatic discharge (ESD) detection circuit configured to generate a control signal having a logic state indicative of detection of an ESD event at said first output of the rectification circuit;
- and
- a control circuit coupled to said control terminal and configured to control said transistor in an off state in response to assertion of the control signal due to detection of the ESD event.
An integrated circuit, comprising:
- a first terminal and a second terminal configured to be coupled to respective antenna terminals;
- a first transistor having a first conduction terminal connected to the first terminal, a second conduction terminal connected to the second terminal, and a control terminal;
- a rectification circuit having first and second inputs coupled to the first and second terminals, respectively, and having first and second outputs;
- an electrostatic discharge (ESD) transistor having a first conduction terminal connected to the first output, a second conduction terminal connected to the second output, and a control terminal;
- and
- an ESD circuit connected to the first and second outputs and configured to sense a ESD event and in response thereto cause the ESD transistor to turn on and simultaneously block the first transistor from turning on.
Dependencies are inferred from the claim text.