THREE-DIMENSIONAL (3D) CARBON NANOTUBE GATE METAL OXIDE (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETS), AND RELATED FABRICATION PROCESSES

A method of fabricating a three-dimensional (3D) field-effect transistor (FET), comprising:

• disposing a dielectric layer disposed on a top surface of a substrate;
• transferring at least one carbon nanotube to a top surface of the dielectric layer to form a carbon nanotube channel structure, wherein the at least one carbon nanotube has a first length and has a first longitudinal axis;
• disposing a channel dielectric layer over the at least one carbon nanotube;
• transferring a second carbon nanotube above the channel dielectric layer and above a portion of the carbon nanotube channel structure to form a carbon nanotube gate having a second longitudinal axis substantially orthogonal to the first longitudinal axis and comprising a first gate side extending in the direction of the second longitudinal axis and a second gate side opposite the first gate side extending in the direction of the second longitudinal axis;
• and
• forming a second dielectric layer above the carbon nanotube gate.

A three-dimensional (3D) field-effect transistor (FET), comprising:

• a substrate comprising a top surface;
• a dielectric layer disposed on the top surface of the substrate;
• a back carbon nanotube gate disposed above the dielectric layer, the back carbon nanotube gate having a first longitudinal axis;
• a semiconductor channel comprising a semiconductor channel structure disposed above the back carbon nanotube gate, the semiconductor channel having a second length and having a second longitudinal axis substantially orthogonal to the first longitudinal axis;
• a first channel dielectric layer disposed between the back carbon nanotube gate and the semiconductor channel;
• a second channel dielectric layer disposed on a top surface of the semiconductor channel;
• and
• a front carbon nanotube gate disposed on a top surface of the second channel dielectric layer, the front carbon nanotube gate having a third longitudinal axis substantially parallel to the first longitudinal axis.

A method of fabricating a three-dimensional (3D) field-effect transistor (FET), comprising:

• disposing a dielectric layer disposed on a top surface of a substrate;
• transferring a back carbon nanotube gate to a top surface of the dielectric layer, the back carbon nanotube gate having a first longitudinal axis;
• disposing a first channel dielectric layer on the back carbon nanotube gate;
• disposing a semiconductor channel structure to a top surface of the first channel dielectric layer to form a semiconductor channel, the semiconductor channel structure having a second longitudinal axis substantially orthogonal to the first longitudinal axis;
• disposing a second channel dielectric layer on a top surface of the semiconductor channel structure;
• and
• transferring a front carbon nanotube gate on a top surface of the second channel dielectric layer, the front carbon nanotube gate having a third longitudinal axis substantially parallel to the first longitudinal axis.