Gate-all-around integrated circuit structures having asymmetric source and drain contact structures

A method of fabricating an integrated circuit structure, the method comprising:

• forming a vertical arrangement of nanowires above a fin;
• forming a gate stack over the vertical arrangement of nanowires;
• forming a first epitaxial source or drain structure at a first end of the vertical arrangement of nanowires, and forming a second epitaxial source or drain structure at a second end of the vertical arrangement of nanowires;
• forming a first conductive contact structure coupled to the first epitaxial source or drain structure, and forming a second conductive contact structure coupled to the second epitaxial source or drain structure, the second conductive contact structure deeper along the fin than the first conductive contact structure.

An integrated circuit structure, comprising:

• a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires;
• a first gate stack over the first vertical arrangement of nanowires;
• a second gate stack over the second vertical arrangement of nanowires;
• first epitaxial source or drain structures at ends of the first vertical arrangement of nanowires;
• second epitaxial source or drain structures at ends of the second vertical arrangement of nanowires;
• a first pair of conductive contact structures coupled to the first epitaxial source or drain structures;
• and
• a second pair of conductive contact structures coupled to the second epitaxial source or drain structures, wherein at least one of the first and second pairs of conductive contact structures is an asymmetric pair of conductive contact structures.