Vertical fin field effect transistor devices with reduced top source/drain variability and lower resistance

A method of forming a fin field effect device, comprising:

• forming a bottom source/drain layer on a substrate;
• forming one or more vertical fins on the bottom source/drain layer and a fin template on each of the one or more vertical fins;
• forming a bottom spacer layer on the bottom source/drain layer;
• forming a gate structure on the bottom spacer layer and at least one of the one or more vertical fins;
• forming a top spacer layer on the at least one gate structure, wherein at least an upper portion of the at least one of the one or more vertical fins is exposed above the top spacer layer;
• forming a top source/drain layer on the top spacer layer and the exposed upper portion of the at least one of the one or more vertical fins;
• forming a sacrificial spacer on opposite sides of the at least one of the one or more fin templates and the top spacer layer;
• and
• removing a portion of the top source/drain layer not covered by the sacrificial spacer to form a top source/drain electrically connected to the at least one of the one or more vertical fins.

A vertical fin field effect transistor device, comprising:

• one or more vertical fins on a substrate;
• a top source/drain electrically connected to at least one of the one or more vertical fins;
• and
• a conductive fill that wraps around the sidewalls of the top source/drain.