Vertical fin field effect transistor with a reduced gate-to-bottom source/drain parasitic capacitance

A vertical fin field effect device, comprising:

• a fin mesa on a substrate;
• a vertical fin on the fin mesa, wherein the fin mesa extends a greater distance from one vertical fin endwall than a distance from the opposite vertical fin endwall;
• an undercut spacer surrounding the fin mesa;
• an isolation plug surrounding the undercut spacer, wherein the height of the isolation plug is less than the height of the undercut spacer;
• and
• a bottom spacer on the top surface of the fin mesa and undercut spacer, and on the top surface of the isolation plug.

A pair of vertical fin field effect devices, comprising:

• a first fin mesa on a substrate;
• a second fin mesa on the substrate adjacent to the first fin mesa;
• a first vertical fin on the first fin mesa, wherein the first fin mesa extends a greater distance from one vertical fin endwall than a distance from the opposite vertical fin endwall of the first vertical fin;
• a second vertical fin on the second fin mesa, wherein the second fin mesa extends a greater distance from one vertical fin endwall than a distance from the opposite vertical fin endwall of the second vertical fin;
• a first undercut spacer surrounding the first fin mesa;
• a second undercut spacer surrounding the second fin mesa, wherein the first undercut spacer is separated from the second undercut spacer by a distance in the range of about 6 nm to about 20 nm;
• a first isolation plug surrounding the first undercut spacer, wherein the height of the isolation plug is less than the height of the first undercut spacer;
• and
• an isolation plug between the second undercut spacer and the first undercut spacer.