Hemt transistor of the normally off type including a trench containing a gate region and forming at least one step, and corresponding manufacturing method

A method for manufacturing a normally off HEMT transistor, the method comprising:

• in a semiconductor heterostructure that includes a first semiconductor layer and a second semiconductor layer arranged on top of the first semiconductor layer, forming a trench that extends through the second semiconductor layer and a portion of the first semiconductor layer;
• forming a gate region of conductive material within the trench;
• and
• within the trench, forming a dielectric layer that coats the gate region and contacts the semiconductor heterostructure, wherein forming the trench includes:
• forming a lateral structure that delimits laterally a part of the trench and forms a first step that includes a first wall and a second wall;
• forming a first recess in the semiconductor heterostructure, the first recess having a bottom delimited by a surface of the semiconductor heterostructure;
• and subsequently
• forming a second recess in the semiconductor heterostructure, starting from the surface of the semiconductor heterostructure, the second recess having a width smaller than the first recess and being delimited at least in part by the first semiconductor layer.

A method for manufacturing normally off heterostructure field-effect transistor (HEMT), the method comprising:

• in a semiconductor heterostructure including a first semiconductor layer and a second semiconductor layer arranged on top of the first layer, forming a trench that extends through the second semiconductor layer and a portion of the first semiconductor layer;
• forming a passivation layer on the second semiconductor layer;
• forming a conductive gate region extending in the trench through the passivation layer and the semiconductor heterostructure;
• and
• forming a dielectric region coating the gate region and contacting the semiconductor heterostructure and the passivation layer, wherein forming the recess includes:
• defining a planar structure on a first side of the trench, the planar structure having a wall that extends from the first semiconductor layer to the passivation region though the second semiconductor layer;
• and
• defining a stepped structure at a second side of the trench opposite to the first side, the stepped structure including first and second step, the first step including a first wall formed by the first semiconductor layer and parallel to the planar structure;
• and the second step includes a second wall formed by the second semiconductor layer and parallel to the planar structure.