A method and related apparatus for reducing gate-induced drain leakage in semiconductor devices

A semiconductor device, comprising:

• a first source/drain region and a second source/drain region disposed in a semiconductor substrate, wherein the first source/drain region is laterally spaced from the second source/drain region;
• a gate electrode disposed over the semiconductor substrate and between the first source/drain region and the second source/drain region;
• a first isolation structure disposed in the semiconductor substrate, wherein the first source/drain region is disposed between the first isolation structure and the gate electrode, and wherein the first isolation structure has a first sidewall and a second sidewall that is opposite the first sidewall;
• a first silicide structure disposed over the first source/drain region, wherein the first silicide structure is disposed between the first isolation structure and the gate electrode;
• and
• a first silicide blocking structure disposed over the semiconductor substrate and the first isolation structure, wherein the first silicide blocking structure extends continuously from the first sidewall to at least the second sidewall.

A semiconductor device, comprising:

• a first source/drain region and a second source/drain region disposed in a semiconductor substrate, wherein the first source/drain region is laterally spaced from the second source/drain region;
• a first gate electrode disposed over the semiconductor substrate and between the first source/drain region and the second source/drain region;
• a first sidewall spacer disposed over the semiconductor substrate and along a first sidewall of the first gate electrode;
• a second sidewall spacer disposed over the semiconductor substrate and along a second sidewall of the first gate electrode opposite the first sidewall;
• a first silicide structure disposed over the first source/drain region;
• a second silicide structure disposed over the second source/drain region;
• a first silicide blocking structure disposed over the semiconductor substrate, wherein a first portion of the first silicide blocking structure extends vertically from the semiconductor substrate along an outer sidewall of the first sidewall spacer, wherein a second portion of the first silicide blocking structure extends laterally a first distance from the first portion to the first silicide structure, and wherein the first portion has a first uppermost surface disposed over a second uppermost surface of the second portion;
• and
• a second silicide blocking structure disposed over the semiconductor substrate, wherein a third portion of the second silicide blocking structure extends vertically from the semiconductor substrate along an outer sidewall of the second sidewall spacer, wherein a fourth portion of the second silicide blocking structure extends laterally the first distance from the third portion to the second silicide structure, and wherein the third portion has a third uppermost surface disposed over a fourth uppermost surface of the fourth portion.