Semiconductor device having gate insulating layer
AssigneeSamsung Electronics Co., Ltd.
InventorKi Hyung Nam
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes gate trench, an upper gate insulating layer on an inner surface of an upper region of the gate trench, a lower gate insulating layer on an inner surface and a lower surface of a lower region of the gate trench and connected to the upper gate insulating layer, a first gate barrier layer on an inner side of the lower gate insulating layer, a gate electrode on an inner side of the first gate barrier layer and configured to fill the lower region of the gate trench, and a gate buried portion on the gate electrode. A diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.
Claims20
A semiconductor device comprising:
- a substrate comprising an upper surface;
- a gate trench on the upper surface of the substrate, the gate trench including an upper region and a lower region,
- the upper region of the gate trench including a first inner surface,
- the lower region of the gate trench including a second inner surface and a lower surface;
- an upper gate insulating layer on the first inner surface;
- a lower gate insulating layer on the second inner surface and the lower surface, the lower gate insulating layer connected to the upper gate insulating layer;
- a first gate barrier layer on a first inner side of the lower gate insulating layer;
- a gate electrode on a second inner side of the first gate barrier layer, the gate electrode filling the lower region of the gate trench;
- and
- a gate buried portion on the gate electrode,
- wherein a diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.
A semiconductor device comprising:
- a substrate comprising an upper surface;
- a gate trench on the upper surface of the substrate, the gate trench including an upper region and a lower region, the upper region including a first inner surface, the lower region including a second inner surface;
- an upper gate insulating layer on the first inner surface of the upper region of the gate trench;
- a lower gate insulating layer on a.) the second inner surface of the lower region of the gate trench and b.) a lower surface of the lower region of the gate trench, the lower gate insulating layer connected to the upper gate insulating layer;
- a first gate barrier layer on an inner side of the lower gate insulating layer;
- a gate electrode on an inner side of the first gate barrier layer, the gate electrode filling the lower region of the gate trench;
- and
- a gate buried portion on the gate electrode,
- wherein a diameter of an outer circumference of an upper end of the first gate barrier layer is greater than a diameter of a lower surface of the gate buried portion.
A semiconductor device comprising:
- a substrate comprising an active region;
- a gate trench configured to extend in one direction on an upper surface of the substrate;
- an upper gate insulating layer on an inner surface of an upper region of the gate trench;
- a lower gate insulating layer on a.) an inner surface of a lower region of the gate trench and b.) a lower surface of a lower region of the gate trench, the lower gate insulating layer connected to the upper gate insulating layer;
- a first gate barrier layer on an inner side of the lower gate insulating layer;
- a gate electrode on an inner side of the first gate barrier layer, the gate electrode configured to fill the lower region of the gate trench;
- a second gate barrier layer;
- and
- a gate buried portion, the second gate barrier layer and the gate buried portion being sequentially stacked on the gate electrode,
- wherein the upper gate insulating layer and the lower gate insulating layer are in the active region,
- an upper end of the first gate barrier layer is positioned at the same level as an upper surface of the gate electrode,
- a lower surface of the second gate barrier layer is positioned at the same level as a lower end of the lower gate insulating layer are positioned, and
- a diameter of an inner circumference of an upper end of the lower gate insulating layer is greater than a diameter of an inner circumference of a lower end of the upper gate insulating layer.
Dependencies are inferred from the claim text.