Semiconductor device and semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsTakashi IZUMIDA, Takeshi SHIMANE, Tadayoshi UECHI
Life of this patent
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Abstract
A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.
Claims20
A semiconductor device comprising:
- a semiconductor layer having a first plane and a second plane opposite to the first plane;
- a gate electrode;
- a gate insulating layer provided between the first plane and the gate electrode;
- and
- a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, the first p-type impurity regions containing boron, carbon, and germanium, the first p-type impurity regions having a bond structure of boron and carbon, the first p-type impurity regions having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and the first p-type impurity regions having a distance between the first p-type impurity regions being a first distance.
A semiconductor device comprising:
- a semiconductor layer having a first plane and a second plane opposite to the first plane;
- a gate electrode;
- a gate insulating layer provided between the first plane and the gate electrode;
- a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, the first p-type impurity regions containing boron and carbon, the first p-type impurity regions having a bond structure of boron and carbon, the first p-type impurity regions having a first boron concentration, the first p-type impurity regions having a first depth in a direction from the first plane toward the second plane, and the first p-type impurity regions having a distance between the first p-type impurity regions being a first distance;
- and
- a pair of second p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, the second p-type impurity regions containing boron, the second p-type impurity regions having a second boron concentration lower than the first boron concentration, the second p-type impurity regions having a second depth smaller than the first depth in the direction from the first plane toward the second plane, and the second p-type impurity regions having a distance between the second p-type impurity regions being a second distance shorter than the first distance.
A semiconductor memory device comprising:
- a semiconductor layer having a first plane and a second plane opposite to the first plane;
- a memory cell array provided on the first plane and including a plurality of memory cells;
- and
- a first transistor including a first gate electrode, a first gate insulating layer provided between the first plane and the first gate electrode, and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the first gate electrode, the first p-type impurity regions containing boron, carbon, and germanium, the first p-type impurity regions having a bond structure of boron and carbon, the first p-type impurity regions having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and the first p-type impurity regions having a distance between the first p-type impurity regions being a first distance.
Dependencies are inferred from the claim text.