SCALABLE CIRCUIT-UNDER-PAD DEVICE TOPOLOGIES FOR LATERAL GaN POWER TRANSISTORS

A semiconductor device structure comprising:

• a lateral GaN transistor structure comprising active regions for a plurality of transistor sections of a multi-section transistor;
• each transistor section comprising source, drain and gate electrodes defined on the respective active region;
• a level of on-chip metallization defining for each section a contact structure comprising a drain pad and a source pad;
• the drain pad and source pad extending over the active region;
• the drain pad being interconnected by conductive micro-vias to underlying drain electrodes and the source pad being interconnected by conductive micro-vias to underlying source electrodes;
• wherein the drain electrodes have a first cross-section and the source electrodes have a second cross-section greater than the first cross-section, and wherein the drain pad has an area larger than an area of the source pad, areas of the drain pad and the source pad being sized in proportion to said first and second cross-sections.

A semiconductor device structure comprising a lateral GaN (gallium nitride) power transistor comprising:

• a substrate comprising a device area of the transistor;
• a nitride semiconductor layer formed on the device area of the substrate, the nitride semiconductor layer comprising a GaN heterostructure defining active regions for a plurality of transistor sections of a multi-section transistor;
• a first level of on-chip metallization (M1), M1 being patterned to define source, drain and gate finger electrodes of each transistor section and a gate bus;
• for each section, the gate bus comprising a first portion formed on an inactive region along a first edge of the active region, and second portions of the gate bus extending from the first portion of the gate bus and formed on inactive regions between active regions of each section;
• in each section, the source and drain finger electrodes being arranged as an array with the gate finger electrodes running in channel regions between adjacent source and drain finger electrodes, and the gate finger electrodes being interconnected to adjacent second portions of the gate bus;
• an overlying second level of on-chip metallization (M2), M2 being patterned to define for each section a contact structure comprising a drain pad and first and second source contact areas, in each section the drain pad extending laterally in a width direction over a central part of the active region, and the first and second source contact areas being located each side of the drain pad;
• the source contact areas comprising parts of a source bus;
• the source bus comprising first and second portions extending over the underlying first and second portions of the gate bus for the section;
• an intermetal dielectric layer provided between the first and second level metallization M1 and M2;
• the drain pad being interconnected by conductive micro-vias through the intermetal dielectric layer to underlying drain finger electrodes;
• and
• the source finger electrodes being connected laterally to said second portions of the source bus.