Germanium-rich nanowire transistor with relaxed buffer layer

A CMOS transistor structure comprising:

• a substrate comprising silicon;
• a layer of buffer material on the substrate, the buffer material comprising silicon and germanium with germanium from 20 to 45 atomic percent and having a lattice that is at least 75% relaxed with respect to the substrate;
• a first source and a first drain on top of the layer of buffer material;
• a first body comprising monocrystalline silicon and extending between the first source and the first drain;
• a second source and a second drain on top of the layer of buffer material;
• a second body extending between the second source and the second drain, the second body comprising silicon and germanium with a germanium concentration from 40 to 85 atomic percent;
• and
• a gate structure wrapped around the first body and around the second body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the first body and the gate electrode and between the second body and the gate electrode.

A method of fabricating a nanowire transistor, the method comprising:

• providing a substrate comprising monocrystalline silicon;
• forming on the substrate a layer of buffer material with a thickness less than 200 nm, the layer of buffer material comprising silicon and germanium with germanium from 20 to 45 atomic percent and having a lattice structure that is at least 75% relaxed relative to the substrate;
• forming a layer stack over the layer buffer material, the layer stack including alternating layers of a first material comprising silicon and a second material comprising silicon and germanium, wherein the second material contains germanium in an amount from 30 to 85 atomic percent;
• etching the layer stack to define one or more fins;
• processing each of the one or more fins to include nanowires between a source and a drain;
• and
• forming a gate structure that is wrapped around the nanowires, the gate structure including a gate electrode and a gate dielectric between each of the nanowires and the gate electrode.