Back to results
US 2020/0091286 A1Published application
Semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsJung-Han LEE, Jae-Hwan LEE, Sang-Su KIM, Hwan-Wook CHOI, Tae-Jong LEE, Seung-Mo HA
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
Claims20
A semiconductor device comprising:
- a substrate;
- a plurality of active fins disposed on the substrate and including a first fin and a second fin;
- an isolation layer disposed on the substrate and disposed between the first fin and the second fin;
- a gate structure disposed on the plurality of active fins and the isolation layer, and including a gate insulation pattern and a gate electrode disposed on the gate insulation pattern, the gate insulation pattern covering a bottom surface and a sidewall of the gate electrode;
- a first gate spacer disposed on a sidewall of gate structure;
- and
- a second gate spacer disposed on a sidewall of the first gate spacer,
- wherein the gate structure includes a first portion disposed on the first fin and a second portion disposed on the isolation layer,
- a width of a lower portion of the first portion of the gate structure is the same as a width of an upper portion of the first portion of the gate structure,
- a width of a lower portion of the second portion of the gate structure is greater than a width of an upper portion of the second portion of the gate structure, and
- a thickness of a first portion of the first gate spacer is greater than a thickness of a second portion of the first gate spacer.
8 more elements
A semiconductor device comprising:
- a substrate;
- a plurality of active fins disposed on the substrate and including a first fin and a second fin;
- an isolation layer disposed on the substrate and disposed between the first fin and the second fin;
- a gate structure disposed on the plurality of active fins and the isolation layer, and including a gate insulation pattern and a gate electrode disposed on the gate insulation pattern, the gate insulation pattern covering a bottom surface and a sidewall of the gate electrode;
- a first gate spacer disposed on a sidewall of gate structure;
- and
- a second gate spacer disposed on a sidewall of the first gate spacer,
- wherein the gate structure includes a first portion disposed on the first fin and a second portion disposed on the isolation layer,
- a width of a lower portion of the first portion of the gate structure is the same as a width of an upper portion of the first portion of the gate structure,
- a width of a lower portion of the second portion of the gate structure is different from a width of an upper portion of the second portion of the gate structure,
- the first gate spacer includes a first portion disposed on the first fin and a second portion disposed on the isolation layer, and
- a bottom surface of the second portion of the first gate spacer is disposed higher than a bottom surface of the second portion of the gate structure.
9 more elements
A semiconductor device comprising:
- a substrate;
- a plurality of active fins disposed on the substrate and including a first fin and a second fin;
- an isolation layer disposed on the substrate and disposed between the first fin and the second fin;
- a gate structure disposed on the plurality of active fins and the isolation layer, and including a gate insulation pattern and a gate electrode disposed on the gate insulation pattern, the gate insulation pattern covering a bottom surface and a sidewall of the gate electrode;
- and
- a first gate spacer disposed on a sidewall of gate structure,
- wherein the gate structure includes a first portion disposed on the first fin and a second portion disposed on the isolation layer,
- a width of a lower portion of the first portion of the gate structure is the same as a width of an upper portion of the first portion of the gate structure,
- a width of a lower portion of the second portion of the gate structure is different from a width of an upper portion of the second portion of the gate structure,
- the first gate spacer includes a first portion disposed on the first fin and a second portion disposed on the isolation layer,
- a bottom surface of the second portion of the first gate spacer is disposed higher than a bottom surface of the second portion of the gate structure,
- the second portion of the gate electrode includes a corner portion where a sidewall of second portion of the gate electrode and the bottom surface of second portion of the gate electrode meet,
- the corner portion of the second portion of the gate electrode is rounded,
- a thickness of a first sub-portion of the second portion of the first gate spacer is greater than a thickness of a second sub-portion of the second portion of the first gate spacer, and
- the second sub-portion of the second portion of the first gate spacer is disposed on the first sub-portion of the second portion of the first gate spacer.
12 more elements
Dependencies are inferred from the claim text.